參數(shù)資料
型號(hào)： V58C2512404SAT5I
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.65 ns, PDSO66
封裝： 0.400 X 0.875 INCH, PLASTIC, MS-024FC, TSOP2-66
文件頁(yè)數(shù)： 60/60頁(yè)
文件大?。?/td> 914K
代理商： V58C2512404SAT5I
9
ProMOS TECHNOLOGIES
V58C2512(804/404/164)SA*I
V58C2512(804/404/164)SA*I Rev. 1.6 May 2007
Functional Description
■ Power-Up Sequence
The following sequence is required for POWER UP.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.
4. Precharge all banks.
5. Issue EMRS to enable DLL.(To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0
and “Low” to all of the rest address pins, A1~A11 and BA1)
6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is
required to lock the DLL. (To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command to initialize device operation.
Note1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it,
the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Extended Mode Register Set (EMRS)
The extended mode register stores the data for enabling or disabling DLL. The default value of the extend-
ed mode register is not defined, therefore the extended mode register must be written after power up for en-
abling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and
high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into
the extended mode register). The state of address pins A0 ~ A11 and BA1 in the same cycle as CS, RAS,
CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used
for DLL enable or disable. “High” on BA0 is used for EMRS. All the other address pins except A0 and BA0
must be set to low for proper EMRS operation. A
1 is used at EMRS to indicate I/O strength A1 = 0 full strength,
A
1 = 1 half strength. Refer to the table for specific codes.
Power up Sequence & Auto Refresh(CBR)
Command
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tRP
2 Clock min.
precharge
ALL Banks
2nd Auto
Refresh
Mode
Register Set
Any
Command
tRFC
1st Auto
Refresh
tRFC
min. 200 Cycle
CK, CK
EMRS
MRS
2 Clock min.
200
S Power up
to 1st command
DLL Reset
2 Clock min.
6
5
47
8
precharge
ALL Banks
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