參數(shù)資料
型號(hào)： V58C2512404SAT5I
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.65 ns, PDSO66
封裝： 0.400 X 0.875 INCH, PLASTIC, MS-024FC, TSOP2-66
文件頁(yè)數(shù)： 29/60頁(yè)
文件大?。?/td> 914K
代理商： V58C2512404SAT5I
35
ProMOS TECHNOLOGIES
V58C2512(804/404/164)SA*I
V58C2512(804/404/164)SA*I Rev. 1.6 May 2007
IDD Max Specifications and Conditions
(-40°C < TA < +85°C, VDDQ=2.5V+ 0.2V, VDD=2.5 +0.2V, for DDR400 device VDDQ=2.6V+ 0.1V, VDD=2.6 +0.1V)
Conditions
Version
Symbol
-5
-6
Unit
Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz
for DDR266A & DDR266B, 166Mhz for DDR333B; DQ,DM and DQS inputs changing twice per clock
cycle; address and control inputs changing once per clock cycle
IDD0
180
170
mA
Operating current - One bank operation; One bank open, BL=4
IDD1
200
190
mA
Precharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max);
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
IDD2P
10
mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min);
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; Vin = Vref for DQ,DQS and DM
IDD2F
50
mA
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK =
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable with
keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
IDD2Q
88
74
mA
Active power - down standby current; one bank active; power-down mode; CKE=< VIL (max); tCK
= 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166MHZ for DDR333B; Vin = Vref for
DQ,DQS and DM
IDD3P
50
mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge;
tRC=tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B, 166Mhz for
DDR333B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs
changing once per clock cycle
IDD3N
80
60
mA
Operating current - burst read; Burst length = 2; reads; continuous burst; One bank active; address
and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK =
133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B, CL=2.5 at tCK=166Mhz for DDR333B;
50% of data changing at every burst; lout = 0 m A
IDD4R
230
210
mA
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address
and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK =
133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing
twice per clock cycle, 50% of input data changing at every burst
IDD4W
270
230
mA
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A
& DDR266B at 133Mhz, 12*tCK for DDR333B; distributed refresh
IDD5
400
380
mA
Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz
for DDR266A & DDR266B, 166Mhz for DDR333B.
Self refresh current; (Low Power)
IDD6
(normal)
55
mA
(L)
3
mA
Operating current - Four bank operation; Four bank interleaving with BL=4
IDD7
650
600
mA
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