- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383985 > USB97C201-MC (STANDARD MICROSYSTEMS CORP) USB 2.0 ATA/ ATAPI Controller PDF資料下載
參數(shù)資料
| 型號： | USB97C201-MC |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | USB 2.0 ATA/ ATAPI Controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 46/59頁 |
| 文件大小： | 385K |
| 代理商： | USB97C201-MC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁當(dāng)前第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
SMSC DS – USB97C201
Page 46
Rev. 03/25/2002
PRELIMINARY
The first data port read of a sector is called the demand read. Subsequent data port reads from the sector are called
prefetch reads. The demand read and all prefetch reads must be of the same size (16 or 32 bits).
Data posting is performed for writes to the IDE data ports. The IDE CONTROLLER will then run the IDE cycle to
transfer the data to the drive.
6.3.4
DMA TRANSFERS
When enabled and supported by the device, DMA transfers are executed on the IDE interface, the chip selects
(IDE_nCS1/0) will be negated (high). When the IDE device asserts IDE_DRQ, the IDE Controller will return
IDE_nDACK to the IDE device when it is ready for the DMA data transfer. For multiword DMA transfers, the
IDE_nIOR or IDE_nIOW signal will free run at the programmed rate as long as IDE_DRQ remains asserted and the
IDE Controller is prepared to complete a data transfer. If IDE_DRQ has not de-asserted by the rising edge of
IDE_nIOR or IDE_nIOW signal multiword DMA is assumed and at least one more cycle will be executed. If
IDE_DRQ de-asserts before IDE_nIOR or IDE_nIOW is de-asserted while IDE_nDACK is asserted, it indicates that
one last data transfer remains for the current session. In this case, IDE_nDACK will be de-asserted one clock after
the IDE_nIOR or IDE_nIOW signal de-asserts. This allows the IDE controller to support both single and multiword
DMA cycles automatically.
The IDE device’s DMA request signal is sampled when the IO strobe is deasserted. If inactive, the DMA
Acknowledge signal is deasserted and no more transfers take place until DMA request is again asserted.
The controller transfers data to or from the EP2 buffer(s) responding to the DMA requests from the IDE device. The
controller will continue this until stopped or the byte count in ATA_CNT[3:0] reaches zero.
6.3.4.1
Completion of DMA Data Transfers
The IDE device signals an interrupt (IDE_IRQ) once its programmed data count has been transferred or an error
occurs. The IDE device will also deassert its DMA request signal, causing the IDE Controller to stop transferring
data. On reads from the IDE device, it will cause any data read from the device to be transferred to the EP2 buffer(s),
as they become available.
6.3.5
Ultra ATA/66 is a new IDE transfer protocol used to transfer data between a Ultra ATA/66 capable IDE controller and
Ultra ATA/66 capable IDE devices. Ultra DMA/66 utilizes a “source synchronous” signaling protocol to transfer data
at rates up to 66 Mbytes/sec.
ULTRA ATA/66 SYNCHRONOUS DMA OPERATION
6.3.5.1
Although no additional signal pins are required for Ultra ATA/66 operation, the operation of some standard IDE
controller pins are redefined during Ultra ATA modes of operation. The Ultra DMA/66 protocol defines three hand-
shaking signals: STOP, STROBE and DMARDY. Table 63 shows the mapping of the redefined Ultra ATA/66 signals
onto the standard IDE controller pins.
Ultra ATA/66 Signals
STOP:
STOP is always driven by the the USB97C201 and is used to request that a transfer be stopped or as an
acknowledgment to stop a request from IDE device. The IDE_nIOW signal is redefined as STOP for both read and
write transfers.
STROBE
: This is a data strobe signal driven by the TRANSMITTER of a data transfer, which is either the IDE device
of a DMA Read transfer or the USB97C201 of a DMA Write transfer, on which data is transferred during each rising
and falling edge transition of the signal. The IORDY signal is redefined as STROBE for reads (when transferring data
from the IDE device to the USB97C201). The IDE_nIOR signal is redefined as STROBE for writes (transferring data
from the USB97C201 to the IDE device).
nDMARDY:
This is a signal driven by the RECEIVER of a data transfer, which is either the USB97C201 of a DMA
Read transfer or the IDE device of a DMA Write transfer, to signal that the RECEIVER is ready to transfer data or to
add wait states to the current transaction. The IDE_nIOR signal is redefined as nDMARDY for reads (when
transferring data from the IDE device to the USB97C201). The IORDY signal is redefined as nDMARDY for writes
(transferring data from the USB97C201 to the IDE device).
Table 63 – ULTRA ATA/66 Control Signal Assignments
SIGNAL NAME
DURING ULTRA
ATA/66 READ
STANDARD
IDE SIGNAL
SIGNAL NAME
DURING ULTRA
ATA/66 WRITE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| USB97C201-MN | USB 2.0 ATA/ ATAPI Controller |
| USB97CFDC-MN | USB FLOPPY DISK CONTROLLER |
| USB97C202 | ATA/ATAPI CONTROLLER |
| USB97C202-MN-02 | ATA/ATAPI CONTROLLER |
| USB97C223 | capacitor Selection for Internal Regulator Output Pins |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| USB97C201-MN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述: |
| USB97C202 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller |
| USB97C202_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller |
| USB97C202-MN-02 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| USB97C202-MN-04 | 制造商:Rochester Electronics LLC 功能描述:USB 2.0 ATA/ATAPI PERI CNTRLR - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。