參數(shù)資料
型號(hào)： USB97C201-MC
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 總線控制器
英文描述： USB 2.0 ATA/ ATAPI Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： QFP-100
文件頁數(shù)： 21/59頁
文件大?。?/td> 385K
代理商： USB97C201-MC
SMSC DS – USB97C201
Page 21
Rev. 03/25/2002
PRELIMINARY
Table 9 - Interrupt 1 Mask
IMR_1
(0x94- RESET=0xFF)
NAME
ZLP_EP0
INTERRUPT 1 MASK REGISTER
DESCRIPTION
Zero Length Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Reserved. This bit should never be written to a “0”.
ATA PIO Complete Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 1 Received Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 1 Transmitted Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 0 Received Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
Endpoint 0 Transmitted Packet Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
SUSPEND Interrupt Mask
0 = Enable Interrupt
1 = Mask Interrupt
BIT
7
R/W
R/W
6
5
Resereved
ATA_PIO
R/W
R/W
4
EP1RX
R/W
3
EP1TX
R/W
2
EP0RX
R/W
1
EP0TX
R/W
0
SUSPEND
R/W
Note 1:
The mask bits do not prevent the status in the ISR_1 register from being set, only from generating an
interrupt.
Table 10 - Device Revision Register
DEV_REV
(0x95- RESET=0xXX)
DEVICE REVISION REGISTER
DESCRIPTION
This register defines additional revision information
used internally by SMSC. The value is silicon revision
dependent.
BIT
[7:0]
R/W
R
XXh
Table 11 - Device Identification Register
DEV_ID
(0x96- RESET=0x12)
DEVICE IDENTIFICATION REGISTER
DESCRIPTION
This register defines additional revision information
used internally by SMSC
BIT
[7:0]
R/W
R
12h
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
USB97C201-MN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
USB97C202 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller
USB97C202_07 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller
USB97C202-MN-02 制造商:Rochester Electronics LLC 功能描述:- Bulk
USB97C202-MN-04 制造商:Rochester Electronics LLC 功能描述:USB 2.0 ATA/ATAPI PERI CNTRLR - Bulk
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