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參數(shù)資料
| 型號： | USB97C201-MC |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | USB 2.0 ATA/ ATAPI Controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 30/59頁 |
| 文件大?。?/td> | 385K |
| 代理商： | USB97C201-MC |
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SMSC DS – USB97C201
Page 30
Rev. 03/25/2002
PRELIMINARY
Table 26 - USB Bus Status Register
USB_STAT
(0xAB - RESET=0x00)
NAME
Reserved
EP2_ERR
USB BUS STATUS REGISTER
DESCRIPTION
This bit always reads “0”.
1 = Indicates that a token in the opposite direction inferred
by the DIR bit of EP2_CTL register was received, ie an
unexpected IN or OUT token.
1 = Host is high speed capable. This bit is set if high speed
signaling is received from the host.
1 = Indicates that RESUME signaling has been detected.
This is only valid if the USB97C201 is in the SUSPEND
state via bit 0 of the SIE_CONF register.
1 = Indicates that a USB Reset has been detected.
1 = Indicates that a USB Error has been detected. See the
USB_ERR register for details. This bit is cleared by clearing
the USB_ERR register.
This bit always reads “0”.
This bit always reads “0”.
BIT
[7]
6
R/W
R
R/W
5
2.0
R/W
4
USB_RESUME
R/W
3
2
USB_RESET
ERROR
R/W
R
1
0
Reserved
Reserved
R
R
The bits in this register (except bit 2) are cleared by writing a ‘1’ to the corresponding bit. These bits are ORed, if
unMASKED in the USB_MSK register, and drive a latch for the USB_STAT bit in the ISR_0 register.
Table 27 – USB Bus Status Mask Register
USB_MSK
(0xAC - RESET=0xFF)
NAME
Reserved
EP2_ERR
USB BUS STATUS MASK REGISTER
DESCRIPTION
This bit always reads “1”.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the EP2_ERR bit is set in the USB_STAT
register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the 2.0 bit is set in the USB_STAT register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the USB_RESUME bit is set in the
USB_STAT register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the USB_RESET bit is set in the USB_STAT
register.
1 = Prevents generation of the USB_STAT bit in the ISR_0
register when the ERROR bit is set in the USB_STAT
register.
This bit always reads “1”.
This bit always reads “1”.
BIT
[7]
6
R/W
R
R/W
5
2.0
R/W
4
USB_RESUME
R/W
3
USB_RESET
R/W
2
ERROR
R/W
1
0
Reserved
Reserved
R
R
Note1:
The mask bits do not prevent the status in the USB_STAT register from being set, only from setting the
USB_STAT bit in the ISR_0 register.
相關PDF資料 |
PDF描述 |
|---|---|
| USB97C201-MN | USB 2.0 ATA/ ATAPI Controller |
| USB97CFDC-MN | USB FLOPPY DISK CONTROLLER |
| USB97C202 | ATA/ATAPI CONTROLLER |
| USB97C202-MN-02 | ATA/ATAPI CONTROLLER |
| USB97C223 | capacitor Selection for Internal Regulator Output Pins |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| USB97C201-MN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述: |
| USB97C202 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller |
| USB97C202_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller |
| USB97C202-MN-02 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| USB97C202-MN-04 | 制造商:Rochester Electronics LLC 功能描述:USB 2.0 ATA/ATAPI PERI CNTRLR - Bulk |
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