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參數(shù)資料
| 型號： | UPD98409GN-LMU |
| 廠商： | NEC Corp. |
| 英文描述： | ATM LIGHT SAR CONTROLLER |
| 中文描述： | 自動柜員機燈特區(qū)控制器 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大小： | 402K |
| 代理商： | UPD98409GN-LMU |
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10
μ
PD98409
1.3 Serial EEPROM Interface Pins
The
μ
PD98409 has an interface for serial EEPROM supporting the MICROWIRE
TM
interface. Some of the
contents of the PCI configuration register can be loaded from the EEPROM connected.
As the EEPROM, “NM93C46L” of National Semiconductor Corp. is recommended.
Pin Name
Pin No.
I/O
I/O Level
Function
E2PCS
84
O
TTL
EEPROM chip select.
A chip select signal for EEPROM.
Leave this pin open when it is not used.
E2PDI
83
I
TTL
Internally
pulled up
EEPROM data input.
This pin is connected to the data output pin of the EEPROM.
Pull up or open this pin when it is not used.
E2PDO
82
O
TTL
EEPROM data output.
This pin is connected to the data input pin of the EEPROM.
Pull up or open this pin when it is not used.
E2PCLK
79
O
TTL
EEPROM clock.
This pin supplies a clock necessary for data transfer with the
EEPROM.
It outputs the clock input to the BUSCLK pin divided by 36.
Leave this pin open when it is not used.
1.4 JTAG Boundary Scan Pins
(These functions can be supported by request.)
Pin Name
Pin No.
I/O
I/O Level
Function
JDI
216
I
LV-TTL
JTAG Test Data Input.
The JDI pin is used to input data to the JTAG boundary scan circuit
register.
Normally, fix this pin to high or low level.
JDO
217
O
3-state
TTL
JTAG Test Data Output.
The JDO pin is used to output data from the JTAG boundary scan
circuit register. It changes output at the falling edge of the clock input
to the JCK pin.
Normally, leave this pin open.
JCK
214
I
LV-TTL
JTAG Test Clock.
This pin is used to supply a clock to the JTAG boundary scan circuit
register.
Normally, fix this pin to a high or low level.
JMS
218
I
LV-TTL
JTAG Test Mode Select.
Normally, fix this pin to a high or low level.
JRST_B
219
I
LV-TTL
JTAG Test Reset.
This pin initializes the JTAG boundary scan circuit register. Normally,
fix this pin to a low level.
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