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參數(shù)資料
| 型號： | UPD98409GN-LMU |
| 廠商： | NEC Corp. |
| 英文描述： | ATM LIGHT SAR CONTROLLER |
| 中文描述： | 自動柜員機燈特區(qū)控制器 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大?。?/td> | 402K |
| 代理商： | UPD98409GN-LMU |
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The information in this document is subject to change without notice.
MOS INTEGRATED CIRCUIT
μ
PD98409
ATM LIGHT SAR CONTROLLER
1997, 1998
Document No. S12775EJ2V0DS00 (2nd edition)
Date Published May 1998 N CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
DESCRIPTION
The
μ
PD98409 (NEASCOT-S40C
cells. Provided with a PCI (Peripheral Component Interconnect) bus interface control memory and supporting a
MPEG packet transfer engine function to mitigate the workload of the CPU in transferring compressed image data,
this chip has ideal specifications for use in a set top box (STB) to interface with an ATM network. The
μ
PD98409
conforms to ATM Forum recommendations and has AAL5-SAR sublayer and ATM layer functions.
TM
) is a high-performance SAR chip for segmentation and reassembly of ATM
FEATURES
Conforms to ATM Forum
PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz)
Conforms to PCI Local Bus Specification Revision 2.1
AAL-5 SAR sublayer and ATM layer functions
Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software)
Supports up to 64 virtual channels (VC) (64-VC control memory)
Two traffic shapers for transmission scheduling
MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU
Receive FIFO of 12 cells
PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake)
JTAG boundary scan test functions
0.35-
μ
m CMOS process, +5/+3.3-V power supply
- Bus interface +5 V : +5/+3.3-V power supply
- Bus interface +3.3 V: +3.3-V single power supply
ORDERING INFORMATION
Part Number
μ
PD98409GN-LMU
Package
240-pin plastic QFP (0.5-mm fine pitch) (32
×
32 mm)
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