
APPENDIX B LIST OF CAUTIONS
User’s Manual U17854EJ9V0UD
834
(10/33)
Chapter
Cl
assi
fi
cati
on
Function
Details of
Function
Cautions
Page
Chapter
6
Soft
Operation
of
plural
channels
of
timer
array unit
Multiple PWM
output function
To rewrite both TDR0n of the master channel and TDR0p of the slave channel 1, write
access is necessary at least twice. Since the values of TDR0n and TDR0p are loaded
to TCR0n and TCR0p after INTTM0n is generated from the master channel, if
rewriting is performed separately before and after generation of INTTM0n from the
master channel, the TO0p pin cannot output the expected waveform. To rewrite both
TDR0n of the master and TDR0p of the slave, be sure to rewrite both the registers
immediately after INTTM0n is generated from the master channel (This applies also to
TDR0q of the slave channel 2) .
p.254
When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (fSUB) is stable. If RTCEN = 0, writing to a control register of the real-
time counter is ignored, and, even if the register is read, only the default value is read.
p.264
PER0: Peripheral
enable register 0
Be sure to clear bit 1, 6 of the PER0 register to 0.
p.264
RTCC0: Real-
time counter
control register 0
If RCLOE0 and RCLOE1 are changed when RTCE = 1, glitches may occur in the
32.768 kHz and 1 Hz output signals.
p.265
RTCC1: Real-
time counter
control register 1
The RIFG and WAFG flags may be cleared when the RTCC1 register is written by
using a 1-bit manipulation instruction. Use, therefore, an 8-bit manipulation instruction
in order to write to the RTCC1 register. To prevent the RIFG and WAFG flags from
being cleared during writing, disable writing by setting “1” to the corresponding bit.
When the value may be rewritten because the RIFG and WAFG flags are not being
used, the RTCC1 register may be written by using a 1-bit manipulation instruction.
p.267
Change ICT2, ICT1, and ICT0 when RINTE = 0.
p.268
When the output from RTCDIV pin is stopped, the output continues after a maximum
of two clocks of fXT and enters the low level. While 512 Hz is output, and when the
output is stopped immediately after entering the high level, a pulse of at least one
clock width of fXT may be generated.
p.268
RTCC2: Real-
time counter
control register 2
After the real-time counter starts operating, the output width of the RTCDIV pin may
be shorter than as set during the first interval period.
p.268
When a correction is made by using the SUBCUD register, the value may become
8000H or more.
p.269
This register is also cleared by reset effected by writing the second count register.
p.269
RSUBC: Sub-
count register
The value read from this register is not guaranteed if it is read during operation,
because a value that is changing is read.
p.269
HOUR: Hour
count register
Bit 5 (HOUR20) of HOUR indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
p.270
WEEK: Week
count register
The value corresponding to the month count register or the day count register is not
stored in the week count register automatically.After reset release, set the week count
register as follow.
p.273
ALARMWM:
Alarm minute
register
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the
range is set, the alarm is not detected.
p.276
Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a
value outside the range is set, the alarm is not detected.
p.276
ALARMWH:
Alarm hour
register
Bit 5 (WH20) of ALARMWH indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
p.276
Chapter
7
Soft
Real-time
counter
Reading/writing
real-time counter
Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within
1 second.
pp.280,
281