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CHAPTER 22 RESET FUNCTION
437
User
’
s Manual U14260EJ3V1UD
Table 22-1. Hardware Statuses After Reset Acknowledgment (2/2)
Hardware
Status After Reset
Acknowledgment
Clock output/buzzer output controller
Clock output select register (CKS)
00H
A/D converter
Conversion result register 0 (ADCR0)
0000H
Mode register 0 (ADM0)
00H
Analog input channel specification register 0 (ADS0)
00H
Serial interface UART0
Asynchronous serial interface mode register 0 (ASIM0)
00H
Asynchronous serial interface status register 0 (ASIS0)
00H
Baud rate generator control register 0 (BRGC0)
00H
Transmit shift register 0 (TXS0)
FFH
Receive buffer register 0 (RXB0)
Serial interface UART2
Asynchronous serial interface mode register 2 (ASIM2)
00H
Transfer mode specification register 2 (TRMC2)
02H
Clock select register 2 (CKSEL2)
00H
Baud rate generator control register 2 (BRGC2)
00H
Asynchronous serial interface status register 2 (ASIS2)
00H
Asynchronous serial interface transmit status register 2 (ASIF2)
00H
Transmit buffer register 2 (TXB2)
FFH
Receive buffer register 2 (RXB2)
FFH
Serial interface SIO3
Shift register 3 (SIO3)
Undefined
Operation mode register 3 (CSIM3)
00H
Serial interface CSI1
Transmit buffer register 1 (SOTB1)
Undefined
Shift register 1(SIO1)
Undefined
Operation mode register 1 (CSIM1)
00H
Clock select register 1 (CSIC1)
10H
Serial interface IIC0
Note
Transfer clock select register 0 (IICCL0)
00H
Shift register 0 (IIC0)
00H
Control register 0 (IICC0)
00H
Status register 0 (IICS0)
00H
Slave address register 0 (SVA0)
00H
Interrupt
Request flag registers (IF0L, IF0H, IF1L)
00H
Mask flag registers (MK0L, MK0H, MK1L)
FFH
Priority specification flag registers (PR0L, PR0H, PR1L)
FFH
External interrupt rising edge enable register (EGP)
00H
External interrupt falling edge enable register (EGN)
00H
Note
Provided only in the
μ
PD780078Y Subseries.