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CHAPTER 18 SERIAL INTERFACE IIC0 (
μ
PD780078Y SUBSERIES ONLY)
User
’
s Manual U14260EJ3V1UD
18.5.7 Interrupt request (INTIIC0) generation timing and wait control
The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
and the corresponding wait control, as shown in Table 18-2.
Table 18-2. INTIIC0 Generation Timing and Wait Control
WTIM0
During Slave Device Operation
During Master Device Operation
Address
Data Reception
Data Transmission
Address
Data Reception
Data Transmission
0
9
Notes 1, 2
8
Note 2
8
Note 2
9
8
8
1
9
Notes 1, 2
9
Note 2
9
Note 2
9
9
9
Notes 1.
The slave device
’
s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is output regardless of the value set to IICC0
’
s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the
9th clock, but wait does not occur.
2.
If the received address does not match the contents of slave address register 0 (SVA0) and extension
code is not received, neither INTIIC0 nor a wait occurs.
Remark
The numbers in the table indicate the number of the serial clock
’
s clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
Slave device operation:
Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIM0 bit.
(2) During data reception
Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(3) During data transmission
Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
By setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1
By writing to IIC shift register 0 (IIC0)
By setting a start condition (setting bit 1 (STT0) of IICC0 to 1)
Note
By setting a stop condition (setting bit 0 (SPT0) of IICC0 to 1)
Note
Note
Master only.
When an 8-clock wait has been selected (WTIM0 = 0), the output level of ACK must be determined prior to wait
cancellation.