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您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383984 > UPD780076 (NEC Corp.) 8-Bit Single-Chip Microcontrollers PDF資料下載

型號(hào)：	UPD780076
廠(chǎng)商：	NEC Corp.
元件分類(lèi)：	8位微控制器
英文描述：	8-Bit Single-Chip Microcontrollers
中文描述：	8位單芯片微控制器
文件頁(yè)數(shù)：	342/592頁(yè)
文件大小：	3307K
代理商：	UPD780076

CHAPTER 18 SERIAL INTERFACE IIC0 (

PD780078Y SUBSERIES ONLY)

s Manual U14260EJ3V1UD

Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4)

Stop condition trigger

Stop condition is not generated.

Stop condition is generated (termination of master device

s transfer).

After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to

high level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level

to high level and a stop condition is generated.

Cautions concerning set timing

For master reception:

Cannot be set during transfer.

Can be set only in the waiting period when ACKE0 has been set to 0 and slave has

been notified of final reception.

A stop condition cannot be generated normally during the ACK0 period. Therefore,

set it during the waiting period.

Cannot be set at the same time as STT0.

SPT0 can be set only when in master mode.

When WTIM0 has been set to 0, if SPT0 is set during the wait period that follows output of eight clocks, note

that a stop condition will be generated during the high level period of the ninth clock.

When a ninth clock must be output, WTIM0 should be changed from 0 to 1 during the wait period following

output of eight clocks, and SPT0 should be set during the wait period that follows output of the ninth clock.

For master transmission:

Condition for clearing (SPT0 = 0)

Condition for setting (SPT0 = 1)

Cleared by loss in arbitration

Automatically cleared after stop condition is detected

Set by instruction

Cleared by LREL0 = 1 (exit from communications)

When IICE0 = 0 (operation stop)

When RESET is input

Set SPT0 only in master mode. However, SPT0 must be set and a stop condition generated before the

first stop condition is detected following the switch to the operation enabled status. For details, see

Other cautions

When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set during the ninth clock

and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high impedance.

Bit 0 (SPT0) becomes 0 when it is read after data setting.

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