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參數(shù)資料
| 型號(hào)： | UPD72042GT |
| 廠商： | NEC Corp. |
| 英文描述： | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
| 中文描述： | LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制 |
| 文件頁(yè)數(shù)： | 21/92頁(yè) |
| 文件大?。?/td> | 373K |
| 代理商： | UPD72042GT |
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PD72042
21
Data Sheet S14870EJ1V0DS00
2.5 BIT FORMAT
Fig. 2-4 illustrates the bits that constitute an IEBus communication frame.
Fig. 2-4 IEBus Bit Format (Concept)
Preparation period
Synchronization period
Data period
: First and subsequent low-level (logic 1) periods
: Next high-level (logic 0) period
: Period in which a bit value is indicated (logic 1 = low level, logic 0 = high level)
The synchronization and data periods are almost equal in duration.
For the IEBus, synchronization is established for each bit. The specifications of the total time required for a bit
and the duration of each period allotted within the bit vary depending on the type of the transmission bits, and whether
the unit is a master or slave.
Logic "1"
Logic "0"
Preparation
period
Synchronization
period
Data period
Preparation
period
Synchronization
period
Data period
Logic 1: The potential difference between the bus lines (the BUS+ and BUS- pins) is 20 mV or less (low level).
Logic 0: The potential difference between the bus lines (the BUS+ and BUS- pins) is 120 mV or more (high level).
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