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參數(shù)資料
| 型號(hào)： | UPD720114GA-9EU-A |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁(yè)數(shù)： | 20/32頁(yè) |
| 文件大?。?/td> | 300K |
| 代理商： | UPD720114GA-9EU-A |
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Data Sheet S17462EJ2V0DS
20
μ
PD720114
(3/4)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Hub Event Timings
Time to detect a downstream facing port
connect event (Figure 2-17):
Awake hub
Suspended hub
t
DCNN
2.5
2.5
2000
12000
μ
s
μ
s
Time to detect a disconnect event at a
hub’s downstream facing port (Figure 2-16)
t
DDIS
2.0
2.5
μ
s
Duration of driving resume to a
downstream port (only from a controlling
hub)
t
DRSMDN
20
ms
Time from detecting downstream resume
to rebroadcast
t
URSM
1.0
ms
Duration of driving reset to a downstream
facing port (Figure 2-18)
t
DRST
Only for a SetPortFeature
(PORT_RESET) request
10
20
ms
Time to detect a long K from upstream
t
URLK
2.5
100
μ
s
Time to detect a long SE0 from upstream
t
URLSE0
2.5
10000
μ
s
Duration of repeating SE0 upstream (for
low-/full-speed repeater)
t
URPSE0
23
FS Bit
times
Inter-packet delay (for high-speed) of
packets traveling in same direction
t
HSIPDSD
88
Bit
times
Inter-packet delay (for high-speed) of
packets traveling in opposite direction
t
HSIPDOD
8
Bit
times
Inter-packet delay for device/root hub
response with detachable cable for high-
speed
t
HSRSPIPD1
192
Bit
times
Time of which a Chirp J or Chirp K must be
continuously detected (filtered) by hub or
device during Reset handshake
t
FILT
2.5
μ
s
Time after end of device Chirp K by which
hub must start driving first Chirp K in the
hub’s chirp sequence
t
WTDCH
100
μ
s
Time for which each individual Chirp J or
Chirp K in the chirp sequence is driven
downstream by hub during reset
t
DCHBIT
40
60
μ
s
Time before end of reset by which a hub
must end its downstream chirp sequence
t
DCHSE0
100
500
μ
s
Time from internal power good to device
pulling D
+
beyond V
IHZ
(Figure 2-18)
t
SIGATT
100
ms
Debounce interval provided by USB
system software after attach (Figure 2-18)
t
ATTDB
100
ms
Maximum duration of suspend averaging
interval
t
SUSAVGI
1
s
Period of idle bus before device can initiate
resume
t
WTRSM
5
ms
Duration of driving resume upstream
t
DRSMUP
1
15
ms
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相關(guān)代理商/技術(shù)參數(shù) |
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| UPD720114GA-YEU-A | 功能描述:HOST CTLR USB 2.0 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:ECOUSB™ 標(biāo)準(zhǔn)包裝:2,450 系列:- 控制器類型:SPI 總線至 I²C 總線橋接 接口:I²C，串行，SPI 電源電壓:2.4 V ~ 3.6 V 電流 - 電源:11mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-HVQFN（4x4） 包裝:托盤(pán) 配用:568-3511-ND - DEMO BOARD SPI TO I2C 其它名稱:935286452157SC18IS600IBSSC18IS600IBS-ND |
| UPD720114GA-YEU-ATR | 制造商:Renesas Electronics Corporation 功能描述:I/O CNTRLR USB CNTRLR 48TQFP - Trays |
| UPD720114K9-4E4-A | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 HUB CTRL, 4-PORTS, 40-PIN PLASTIC QFN (6MMX6MM) - Trays |
| UPD720114K9-4E4-SSA-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD720122GC-9EU-A | 制造商:NEC Electronics Corporation 功能描述:IC CONTROLLER USB SMD TQFP100 |
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