參數(shù)資料
型號: UPD720114GA-9EU-A
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 19/32頁
文件大小: 300K
代理商: UPD720114GA-9EU-A
Data Sheet S17462EJ2V0DS
19
μ
PD720114
(2/4)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Full-speed Electrical Characteristics (Continued)
Consecutive frame interval jitter
t
RFI
No clock adjustment
42
ns
Source jitter total (including frequency
tolerance) (Figure 2-13):
To next transition
For paired transitions
t
DJ1
t
DJ2
Note
3.5
4.0
+
3.5
+
4.0
ns
ns
Source jitter for differential transition to
SE0 transition (Figure 2-14)
t
FDEOP
2
+
5
ns
Receiver jitter (Figure 2-15):
To Next Transition
For Paired Transitions
t
JR1
t
JR2
18.5
9
+
18.5
+
9
ns
ns
Source SE0 interval of EOP (Figure 2-14)
t
FEOPT
160
175
ns
Receiver SE0 interval of EOP (Figure 2-14)
t
FEOPR
82
ns
Width of SE0 interval during differential
transition
t
FST
14
ns
Hub differential data delay (Figure 2-11)
(with cable)
(without cable)
t
HDD1
t
HDD2
70
44
ns
ns
Hub differential driver jitter (including cable)
(Figure 2-11):
To next transition
For paired transitions
t
HDJ1
t
HDJ2
3
1
+
3
+
1
ns
ns
Data bit width distortion after SOP (Figure
2-11)
t
FSOP
5
+
5
ns
Hub EOP delay relative to t
HDD
(Figure
2-12)
t
FEOPD
0
15
ns
Hub EOP output width skew (Figure 2-12)
t
FHESK
15
+
15
ns
High-speed Electrical Characteristics
Rise time (10% to 90%)
t
HSR
500
ps
Fall time (90% to 10%)
t
HSF
500
ps
Driver waveform
See Figure 2-9.
High-speed data rate
t
HSDRAT
479.760
480.240
Mbps
Microframe interval
t
HSFRAM
124.9375
125.0625
μ
s
Consecutive microframe interval difference
t
HSRFI
4 high-
speed
Bit
times
Data source jitter
See Figure 2-9.
Receiver jitter tolerance
See Figure 2-4.
Hub data delay (without cable)
t
HSHDD
36 high-
speed
+
4 ns
Bit
times
Hub data jitter
See Figure 2-4, Figure 2-9.
Hub delay variation range
t
HSHDV
5 high-
speed
Bit
times
Note
Excluding the first transition from the Idle state.
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