參數(shù)資料
型號： UPD70F3271YGF-JBT-A
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù)： 91/129頁
文件大小： 8549K
代理商： UPD70F3271YGF-JBT-A
CHAPTER 3 CPU FUNCTION
User’s Manual U16541EJ5V1UD
64
3.3
Operation Modes
The V850ES/SG2 and V850ES/SG2-H have the following operation modes.
(1) Normal operation mode
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
(2) Flash memory programming mode
In this mode, the internal flash memory can be programmed by using a flash memory programmer.
The following products are on-chip flash memory versions of the V850ES/SG2 and V850ES/SG2-H.
μPD70F3261, 70F3261Y, 70F3263, 70F3263Y, 70F3271, 70F3271Y, 70F3273, 70F3273Y, 70F3281,
70F3281Y, 70F3283, 70F3283Y, 70F3263HY, 70F3273HY, 70F3283HY
(3) On-chip debug mode
The V850ES/SG2 and V850ES/SG2-H are provided with an on-chip debug function that employs the JTAG
(Joint Test Action Group) communication specifications and that is executed via an on-chip debug emulator.
The on-chip debug function is provided only in the flash memory versions.
For details, see CHAPTER 31 ON-CHIP DEBUG FUNCTION.
3.3.1
Specifying operation mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, input a low level to the FLMD0/IC pin after the reset status has been released and before the
oscillation stabilization time expires and the firmware operation is completed.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash memory programmer
if a flash memory programmer is connected, but it must be input from an external circuit in the self-programming
mode.
Operation When Reset Is Released
FLMD0
FLMD1
Operation Mode After Reset
L
×
Normal operation mode
H
L
Flash memory programming mode
H
Setting prohibited
Remark
L: Low-level input
H: High-level input
×: Don’t care
<R>
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