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參數(shù)資料
| 型號(hào)： | UPD70F3271YGF-JBT-A |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 60/129頁(yè) |
| 文件大?。?/td> | 8549K |
| 代理商： | UPD70F3271YGF-JBT-A |
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CHAPTER 1 INTRODUCTION
User’s Manual U16541EJ5V1UD
36
1.6.2
Internal units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits
× 16 bits → 32 bits) and a barrel shifter (32
bits) contribute to faster complex processing.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue.
(3) ROM
This is a 640/512/384/256 KB mask ROM or flash memory mapped to addresses 0000000H to
009FFFFH/0000000H to 007FFFFH/0000000H to 005FFFFH/0000000H to 003FFFFH. It can be accessed
from the CPU in one clock during instruction fetch.
(4) RAM
This
is
a
48/40/32/24
KB
RAM
mapped
to
addresses
3FF3000H
to
3FFEFFFH/3FF5000H
to
3FFEFFFH/3FF7000H to 3FFEFFFH/3FF9000H to 3FFEFFFH. It can be accessed from the CPU in one clock
during data access.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiplexed servicing control can be performed.
(6) Clock generator (CG)
A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency
(fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as
the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4 or 8.
The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT.
(7) Internal oscillator
An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP). The internal oscillator
supplies the clock for watchdog timer 2 and timer M.
(8) Timer/counter
Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and one-
channel 16-bit interval timer M (TMM), are provided on chip.
(9) Watch timer
This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the
32.768 kHz clock fBRG from prescaler 3). The watch timer can also be used as an interval timer for the main
clock.
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