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參數(shù)資料
| 型號(hào)： | UPD70F3271YGF-JBT-A |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 22/129頁(yè) |
| 文件大?。?/td> | 8549K |
| 代理商： | UPD70F3271YGF-JBT-A |
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CHAPTER 4 PORT FUNCTIONS
User’s Manual U16541EJ5V1UD
118
4.3.5
Port 5
Port 5 is a 6-bit port that controls I/O in 1-bit units.
Port 5 includes the following alternate-function pins.
Table 4-8. Port 5 Alternate-Function Pins
Pin No.
Pin Name
GF
GC
Alternate-Function Pin Name
I/O
Remark
Block Type
P50
39
37
TIQ01/KR0/TOQ01/RTP00
I/O
U-5
P51
40
38
TIQ02/KR1/TOQ02/RTP01
I/O
U-5
P52
41
39
TIQ03/KR2/TOQ03/RTP02/DDI
Note
I/O
U-6
P53
42
40
SIB2/KR3/TIQ00/TOQ00/RTP03/DDO
Note
I/O
U-7
P54
43
41
SOB2/KR4/RTP04/DCK
Note
I/O
U-8
P55
44
42
SCKB2/KR5/RTP05/DMS
Note
I/O
Selectable as N-ch open-drain output
U-9
Note
The DDI, DDO, DCK, and DMS pins are for on-chip debugging (flash memory version only).
If on-chip debugging is not used, fix the P05/INTP2/DRST pin to low level between when the reset signal of
the RESET pin is released and when the OCDM.OCDM0 bit is cleared (0). Although the mask ROM
versions do not support the on-chip debug mode, an on-chip pull-down resistor is incorporated. Handle the
P05/INTP2 pin the same as the flash memory versions.
For details, see 4.6.3 Cautions on on-chip debug pins.
Cautions 1. When the power is turned on, the P53 pin may momentarily output an undefined level.
2. The P50 to P55 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
Remark
GF: 100-pin plastic QFP (14
× 20)
GC: 100-pin plastic LQFP (fine pitch) (14
× 14)
(1) Port 5 register (P5)
0
Outputs 0
Outputs 1
P5n
0
1
Output data control (in output mode) (n = 0 to 5)
P5
0
P55
P54
P53
P52
P51
P50
After reset: 00H (output latch)
R/W
Address: FFFFF40AH
<R>
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