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| 型號(hào)： | UPD70F3271YGF-JBT-A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 129/129頁(yè) |
| 文件大?。?/td> | 8549K |
| 代理商： | UPD70F3271YGF-JBT-A |
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CHAPTER 4 PORT FUNCTIONS
User’s Manual U16541EJ5V1UD
99
4.3
Port Configuration
Table 4-2. Port Configuration
Item
Configuration
Control register
Port n mode register (PMn: n = 0, 1, 3 to 5, 7, 9, CM, CT, DH, DL)
Port n mode control register (PMCn: n = 0, 3 to 5, 9, CM, CT, DH, DL)
Port n function control register (PFCn: n = 0, 3 to 5, 9)
Port n function control expansion register (PFCEn: n = 3, 5, 9)
Port n function register (PFn: n = 0, 3 to 5, 9)
Ports
I/O: 84
(1) Port n register (Pn)
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Pn7
Output 0.
Output 1.
Pnm
0
1
Control of output data (in output mode)
Pn6
Pn5
Pn4
Pn3
Pn2
Pn1
Pn0
0
1
2
3
7
5
6
7
Pn
After reset: 00H (output latch)
R/W
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Table 4-3. Writing/Reading Pn Register
Setting of PMn Register
Writing to Pn Register
Reading from Pn Register
Output mode
(PMnm = 0)
Data is written to the output latch
Note.
In the port mode (PMCn = 0), the contents of the output
latch are output from the pins.
The value of the output latch is read.
Input mode
(PMnm = 1)
Data is written to the output latch.
The pin status is not affected
Note.
The pin status is read.
Note The value written to the output latch is retained until a new value is written to the output latch.
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