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參數(shù)資料
| 型號： | UPD44647094F5-E30-FQ1 |
| 元件分類： | SRAM |
| 英文描述： | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大小： | 479K |
| 代理商： | UPD44647094F5-E30-FQ1 |
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11
Preliminary Data Sheet M18526EJ1V0DS
μPD44647094,44647184,44647364, 44647096,44647186,44647366
Truth Table
2.0 Cycle Read Latency
[
μPD44647094], [μPD44647184], [μPD44647364]
Operation
CLK
R#
W#
D or Q
WRITE cycle
L
→ H
H
L
Data in
Load address, input write data on two
Input data
DA(A+0)
DA(A+1)
DA(A+2)
DA(A+3)
consecutive K and K# rising edge
Input clock
K(t+1)
↑
K#(t+1)
↑
K(t+2)
↑
K#(t+2)
↑
READ cycle
L
→ H
L
X
Data out
Load address, read data on two
Output data
QA(A+0)
QA(A+1)
QA(A+2)
QA(A+3)
consecutive K and K# rising edge
Output clock
K(t+2)
↑
K#(t+2)
↑
K(t+3)
↑
K#(t+3)
↑
NOP (No operation)
L
→ H
H
D = X, Q = High-Z
Clock stop
Stopped
X
Previous state
2.5 Cycle Read Latency
[
μPD44647096], [μPD44647186], [μPD44647366]
Operation
CLK
R#
W#
D or Q
WRITE cycle
L
→ H
H
L
Data in
Load address, input write data on two
Input data
DA(A+0)
DA(A+1)
DA(A+2)
DA(A+3)
consecutive K and K# rising edge
Input clock
K(t+1)
↑
K#(t+1)
↑
K(t+2)
↑
K#(t+2)
↑
READ cycle
L
→ H
L
X
Data out
Load address, read data on two
Output data
QA(A+0)
QA(A+1)
QA(A+2)
QA(A+3)
consecutive K and K# rising edge
Output clock
K#(t+2)
↑
K(t+3)
↑
K#(t+3)
↑
K(t+4)
↑
NOP (No operation)
L
→ H
H
D = X, Q = High-Z
Clock stop
Stopped
X
Previous state
Remarks
Remarks listed below are for both products with 2.0 and 2.5 Cycle Read Latency.
1. H : HIGH, L : LOW,
× : don’t care, ↑ : rising edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at K and K# rising edges.
3. R# and W# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at
the rising edge of K.
4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# when clock is stopped. This is not essential but permits most rapid restart
by overcoming transmission line charging symmetrically.
7. If R# was LOW to initiate the previous cycle, this signal becomes a don't care for this WRITE operation
however it is strongly recommended that this signal is brought HIGH as shown in the truth table.
8. W# during write cycle and R# during read cycle were HIGH on previous K clock rising edge. Initiating
consecutive READ or WRITE operations on consecutive K clock rising edges is not permitted. The
device will ignore the second request.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44647186AF5-E22-FQ1 | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應商設備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| UPD44647186AF5-E22-FQ1-A | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| UPD44647186AF5-E25-FQ1 | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| UPD44647186AF5-E25-FQ1-A | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
| UPD44647366AF5-E22-FQ1 | 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOIC 包裝:帶卷 (TR) |
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