參數(shù)資料
型號(hào)： UPD44647094F5-E30-FQ1
元件分類： SRAM
英文描述： 8M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, PLASTIC, BGA-165
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 479K
代理商： UPD44647094F5-E30-FQ1
25
Preliminary Data Sheet M18526EJ1V0DS
μPD44647094,44647184,44647364, 44647096,44647186,44647366
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit’s position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
109
bit
ID Register Definition
2.0 Cycle Read Latency
Part number
Organization
ID [31:28] vendor revision no.
ID [27:12] part no.
ID [11:1] vendor ID no. ID [0] fix bit
μPD44647094
8M x 9
XXXX
0000 0000 1001 0101
00000010000
1
μPD44647184
4M x 18
XXXX
0000 0000 1001 0110
00000010000
1
μPD44647364
2M x 36
XXXX
0000 0000 1001 0111
00000010000
1
2.5 Cycle Read Latency
Part number
Organization
ID [31:28] vendor revision no.
ID [27:12] part no.
ID [11:1] vendor ID no. ID [0] fix bit
μPD44647096
8M x 9
XXXX
0000 0000 1010 0001
00000010000
1
μPD44647186
4M x 18
XXXX
0000 0000 1010 0010
00000010000
1
μPD44647366
2M x 36
XXXX
0000 0000 1010 0011
00000010000
1
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UPD44647186AF5-E22-FQ1-A 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
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