參數(shù)資料
型號(hào)： UPD44647094F5-E30-FQ1
元件分類： SRAM
英文描述： 8M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, PLASTIC, BGA-165
文件頁(yè)數(shù)： 1/36頁(yè)
文件大小： 479K
代理商： UPD44647094F5-E30-FQ1
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MOS INTEGRATED CIRCUIT
μPD44647094,44647184,44647364,44647096,44647186,44647366
72M-BIT QDRTM II+ SRAM
2.0 & 2.5 Cycle Read Latency
4-WORD BURST OPERATION
Document No. M18526EJ1V0DS00 (1st edition)
Date Published November 2006 NS CP(N)
Printed in Japan
PRELIMINARY DATA SHEET
2006
Description
The
μPD44647094 and μPD44647096 are 8,388,608-word by 9-bit, the μPD44647184 and μPD44647186 are
4,194,304-word by 18-bit and the
μPD44647364 and μPD44647366 are 2,097,152-word by 36-bit synchronous quad data
rate static RAMs fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μPD44647xx4 is for 2.0 cycle and the μPD44647xx6 is for 2.5 cycle read latency. The μPD44647094,
μPD44647096, μPD44647184, μPD44647186, μPD44647364 and μPD44647366 integrate unique synchronous
peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on
the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
Core (VDD) = 1.8 ± 0.1 V power supply
I/O (VDDQ) = 1.5 ± 0.1 V power supply
165-pin PLASTIC BGA (15x17)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two Echo clocks (CQ and CQ#)
Data Valid pin (QVLD) supported
Read latency : 2.0 & 2.5 clock cycles (Not selectable by user)
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 2,048 cycles after clock is resumed.
User programmable impedance output (35 to 70 Ω)
Fast clock cycle time : 2.66 ns (375 MHz) for 2.0 cycle read latency,
2.5 ns (400 MHz) for 2.5 cycle read latency
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD44647186AF5-E22-FQ1 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8
UPD44647186AF5-E22-FQ1-A 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
UPD44647186AF5-E25-FQ1 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
UPD44647186AF5-E25-FQ1-A 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
UPD44647366AF5-E22-FQ1 功能描述:SRAM QDRII 72MBIT 165-PBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
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