參數(shù)資料
型號: UPD44164362BF5-E40-EQ3-A
元件分類: SRAM
英文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁數(shù): 19/33頁
文件大?。?/td> 494K
代理商: UPD44164362BF5-E40-EQ3-A
μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 26 of 32
Dec 13, 2010
Boundary Scan Register Status of Output Pins CQ, CQ# and DQ
Instructions
SRAM Status
Boundary Scan Register Status
Note
CQ,CQ#
DQ
EXTEST
READ (Low-Z)
Pad
NOP (High-Z)
Pad
IDCODE
READ (Low-Z)
No definition
NOP (High-Z)
SAMPLE-Z
READ (Low-Z)
Pad
NOP (High-Z)
Pad
SAMPLE
READ (Low-Z)
Internal
NOP (High-Z)
Internal
Pad
BYPASS
READ (Low-Z)
No definition
NOP (High-Z)
Remark The Boundary Scan Register statuses during execution each
instruction vary according to the instruction code and SRAM
operation mode.
There are two statuses:
Pad
: Contents of the output pin (DDR Pad) are captured
in the “CAPTURE Register” in the Boundary Scan
Register.
Internal : Contents of the SRAM internal output “SRAM
Output” are captured in the “CAPTURE Register”
in the Boundary Scan Register.
Pad
Internal
SRAM
Output
Driver
Update
Register
DDR
Pad
High-Z
JTAG ctrl
CAPTURE
Register
SRAM
Output
Boundary Scan
Register
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