參數(shù)資料
型號(hào): UPD44164362BF5-E40-EQ3-A
元件分類: SRAM
英文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165
文件頁數(shù): 18/33頁
文件大?。?/td> 494K
代理商: UPD44164362BF5-E40-EQ3-A
μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 25 of 32
Dec 13, 2010
Output Pin States of CQ, CQ# and DQ
Instructions
Control-Register Status
Output Pin Status
CQ,CQ#
DQ
EXTEST
0
Update
High-Z
1
Update
IDCODE
0
SRAM
1
SRAM
SAMPLE-Z
0
High-Z
1
High-Z
SAMPLE
0
SRAM
1
SRAM
BYPASS
0
SRAM
1
SRAM
Remark The output pin statuses during each instruction vary according
to the Control-Register status (value of Boundary Scan
Register, bit no. 109).
There are three statuses:
Update : Contents of the “Update Register” are output to the
output pin (DDR Pad).
SRAM : Contents of the SRAM internal output “SRAM
Output” are output to the output pin (DDR Pad).
High-Z :The output pin (DDR Pad) becomes high
impedance by controlling of the “High-Z JTAG
ctrl”.
The Control-Register status is set during Update-DR at the
EXTEST or SAMPLE instruction.
SRAM
CAPTURE
Register
Boundary Scan
Register
Update
Register
DDR
Pad
SRAM
Output
Driver
High-Z
JTAG ctrl
High-Z
Update
SRAM
Output
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