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CHAPTER 1 INTRODUCTION
User’s Manual U14272EJ3V0UM
46
1.4.10 Code compatibility
The V
R
4110 core is designed in consideration of the program compatibility to other V
R
-Series processors.
However since it has some differences from other processors on their architecture, it cannot necessarily execute all
programs that can be executed in other V
R
-Series processors, and also other V
R
-Series processors cannot
necessarily execute all programs that can be executed in the V
R
4110 core.
Matters that should be paid attention to when porting programs between the V
R
4110 core and other V
R
-Series
processors are listed below.
A 16-bit length MIPS16 instruction set is added in the V
R
4110 core.
Multiply-add instructions (MADD16, DMADD16) are added in the V
R
4110 core.
Instructions for power modes (HIBERNATE, STANDBY, SUSPEND) are added in the V
R
4110 core to support
power modes.
The V
R
4110 core does not support floating-point instructions since it has no Floating-Point Unit (FPU).
The V
R
4110 core does not have the LL bit to perform synchronization of multiprocessing. Therefore, it does not
support instructions that manipulate the LL bit (LL, LLD, SC, SCD).
The CP0 hazards of the V
R
4110 core are equally or less stringent than those of the V
R
4000.
For more information about each instruction, refer to
V
R
4100 Series Architecture User’s Manual
, and user’s
manuals of each product other than the V
R
4100 Series.
Instructions supported by each of the V
R
Series processors are listed below.
Table 1-7. List of Instructions Supported by V
R
Series Processors
Products
Supported instructions
V
R
4181
V
R
4111
V
R
4121
V
R
4122
TM
V
R
4300
TM
V
R
4305
TM
V
R
4310
TM
V
R
5000A
TM
V
R
5432
TM
V
R
10000
TM
V
R
12000
TM
MIPS I
A
A
A
A
A
A
MIPS II
A
A
A
A
A
A
MIPS III
A
A
A
A
A
A
LL bit
manipulation
N/A
N/A
A
A
A
A
MIPS IV
N/A
N/A
N/A
A
A
A
MIPS16
A
A
N/A
N/A
N/A
N/A
Multiply-add
A
(16 bits)
A
(32 bits)
N/A
N/A
A
(32 bits)
N/A
Floating-point operation
N/A
N/A
A
A
A
A
Power mode transition
A
A
N/A
A
A
N/A