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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2)
User’s Manual U14272EJ3V0UM
391
20.3.9 SIUMC_2 (0x0C00 0004)
Bit
7
6
5
4
3
2
1
0
Name
Reserved
Reserved
Reserved
MCR4
MCR3
MCR2
MCR1
MCR0
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
RTCRST
0
0
0
0
0
0
0
0
Other resets
0
0
0
0
0
0
0
0
Bit
Name
Function
7 to 5
Reserved
0 is returned when read
4
MCR4
Use of diagnostic testing (local loopback)
1 : Enable
0 : Disable
3
MCR3
OUT2 signal (internal) setting
1 : Low level
0 : High level
2
MCR2
OUT1 signal (internal) setting
1 : Low level
0 : High level
1
MCR1
RTS2# output control
1 : Low level
0 : High level
0
MCR0
DTR2# output control
1 : Low level
0 : High level
This register is used to control the interface with a modem or data set (or a peripheral device that emulates a
modem).
The settings of the MCR3 and MCR2 bits become valid only when the MCR4 bit is set to 1 (enable use of local
loopback).
Local Loopback
The local loopback can be used to test the transmit/receive data path in SIU2. The following operation (local
loopback) is executed inside the SIU2 when the MCR4 bit = 1.
The transmit block’s serial output (TxD2) enters the marking state (1) and the serial input (RxD2) to the receive
block is cut off. The transmit shift register’s output is looped back to the receive shift register’s input.
The four modem control inputs (DSR2#, CTS2#, RI (internal), and DCD2#) are cut off and the four modem
control outputs (DTR2#, RTS2#, OUT1 (internal), and OUT2 (internal)) are internally connected to the
corresponding modem control inputs. The modem control output pins are forcibly set as inactive (high level).
During this kind of loopback mode, transmitted data can be immediately and directly received.
When in loopback mode, both transmit and receive interrupts can be used. The interrupt sources are external
sources in relation to the transmit and receive blocks. Although modem control interrupts can be used, the low-
order four bits of the modem control register can be used instead of the four modem control inputs as interrupt
sources. As usual, each interrupt is controlled by an interrupt enable register.