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User’s Manual U14272EJ3V0UM
27
LIST OF TABLES (1/2)
Table No.
Title
Page
1-1.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
Supported PClock and TClock Frequencies ...............................................................................................
Devices Supported by System Bus .............................................................................................................
GPIO(31:0) Pin Functions ...........................................................................................................................
LCD Panel Resolutions (in Pixels, TYP.) ....................................................................................................
Functions of LCD Interface Pins when LCD Controller Is Disabled ............................................................
System Control Coprocessor (CP0) Register Definitions ...........................................................................
List of Instructions Supported by V
R
Series Processors .............................................................................
31
31
33
34
34
43
46
3-1.
3-2.
3-3.
3-4.
CP0 Registers .............................................................................................................................................
Cache Algorithm .........................................................................................................................................
Mask Values and Page Sizes .....................................................................................................................
Cause Register Exception Code Field ........................................................................................................
68
71
72
80
4-1.
4-2.
4-3.
4-4.
4-5.
4-6.
V
R
4181 Physical Address Space ................................................................................................................
ROM Address Map .....................................................................................................................................
Internal I/O Space 1 ....................................................................................................................................
Internal I/O Space 2 ....................................................................................................................................
MBA Bus I/O Space ....................................................................................................................................
DRAM Address Map ...................................................................................................................................
93
93
94
94
95
95
6-1.
6-2.
6-3.
6-4.
Bus Control Registers ................................................................................................................................. 110
V
R
4181 EDO DRAM Capacity ..................................................................................................................... 129
Memory Controller Registers ...................................................................................................................... 131
ISA Bridge Registers ................................................................................................................................... 137
7-1.
DCU Registers ............................................................................................................................................ 144
8-1.
CSI Registers .............................................................................................................................................. 160
9-1.
ICU Registers .............................................................................................................................................. 173
10-1.
10-2.
10-3.
10-4.
Overview of Power Modes .......................................................................................................................... 190
Operations During Reset ............................................................................................................................ 191
Operations During Shutdown ...................................................................................................................... 193
PMU Registers ............................................................................................................................................ 208
11-1.
RTC Registers ............................................................................................................................................ 216
12-1.
DSU Registers ............................................................................................................................................ 230
13-1.
13-2.
13-3.
13-4.
Alternate Functions of GPIO(15:0) Pins ...................................................................................................... 236
Alternate Functions of GPIO(31:16) Pins .................................................................................................... 237
CSI Interface Signals .................................................................................................................................. 238
Serial Interface Channel 1 (SIU1) Signals .................................................................................................. 239