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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU)
User’s Manual U14272EJ3V0UM
238
13.1.2 I/O direction control
For each GPIO pin, the GIU provides register fields of one buffer enable, GPENn, one output data, GPOn, and
one input data, GPIn. The function of each GPIO pin is decoded by 2 register bits in one of the GPIO Mode registers.
The most significant bit, GPnMD1, controls the input/output direction of the GPIO pin while the system is powered
(during Fullspeed, Standby, or Suspend mode). When this bit is set to 1, the GPIO pin is normally configured as an
output.
During Hibernate mode, the GPIO buffer enables are controlled by the GPHIBSTH and GPHIBSTL registers.
Remark
n = 0 to 31
13.1.3 General-purpose registers
The GIU includes sixteen 16-bit general-purpose registers. Since the contents of these registers are preserved
even during Hibernate mode, these registers can be used by system software to save the state of selected registers
located in the 2.5 V block prior to entering Hibernate mode. Once the V
R
4181 has resumed from Hibernate mode,
system software can then restore the state of those 2.5 V registers from the general-purpose registers.
The general-purpose registers are located in the address range of 0x0B00 0330 to 0x0B00 034F.
13.2 Alternate Functions Overview
13.2.1 Clocked serial interface (CSI)
The clocked serial interface is enabled by writing to the GPIO Mode registers and utilizes the following GPIO pins:
Table 13-3. CSI Interface Signals
GPIO pin
CSI signal
Type
GPIO2
SCK
Input
GPIO1
SO
Output
GPIO0
SI
Input
GPIO10
FRM
Input
The GPIO10/FRM pin provides a multifunction control input option. In one mode, FRM determines data direction
(transmit or receive). In the other mode, FRM prohibits transfer depending on its input level. This mode is set in bit
15, FRMEN, of the CSIMODE register (address: 0x0B00 0900) (see
CHAPTER 8 CLOCKED SERIAL INTERFACE
UNIT (CSI)
).