參數(shù)資料
型號(hào)： UPD17240MC-XXX-5A4-A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO30
封裝： 0.300 INCH, PLASTIC, SSOP-30
文件頁數(shù)： 79/102頁
文件大小： 668K
代理商： UPD17240MC-XXX-5A4-A
78
Data Sheet U15002EJ1V0DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
Table 12-2. Reserved Symbols (1/3)
Symbol Name
Attribute
Value
R/W
Description
DBF3
MEM
0.0CH
R/W
Bits 15 to 12 of data buffer
DBF2
MEM
0.0DH
R/W
Bits 11 to 8 of data buffer
DBF1
MEM
0.0EH
R/W
Bits 7 to 4 of data buffer
DBF0
MEM
0.0FH
R/W
Bits 3 to 0 of data buffer
AR3
MEM
0.74H
R/W
Bits 15 to 12 of address register
AR2
MEM
0.75H
R/W
Bits 11 to 8 of address register
AR1
MEM
0.76H
R/W
Bits 7 to 4 of address register
AR0
MEM
0.77H
R/W
Bits 3 to 0 of address register
WR
MEM
0.78H
R/W
Window register
BANK
MEM
0.79H
R/W
Bank register
IXH
MEM
0.7AH
R/W
Index register, high
MPH
MEM
0.7AH
R/W
Data memory row address pointer, high
MPE
FLG
0.7AH.3
R/W
Memory pointer enable flag
IXM
MEM
0.7BH
R/W
Index register, middle
MPL
MEM
0.7BH
R/W
Data memory row address pointer, low
IXL
MEM
0.7CH
R/W
Index register, low
RPH
MEM
0.7DH
R/W
General register pointer, high
RPL
MEM
0.7EH
R/W
General register pointer, low
PSW
MEM
0.7FH
R/W
Program status word
BCD
FLG
0.7EH.0
R/W
BCD flag
CMP
FLG
0.7FH.3
R/W
Compare flag
CY
FLG
0.7FH.2
R/W
Carry flag
Z
FLG
0.7FH.1
R/W
Zero flag
IXE
FLG
0.7FH.0
R/W
Index enable flag
P0A0
FLG
0.70H.0
R/W
Bit 0 of port 0A
P0A1
FLG
0.70H.1
R/W
Bit 1 of port 0A
P0A2
FLG
0.70H.2
R/W
Bit 2 of port 0A
P0A3
FLG
0.70H.3
R/W
Bit 3 of port 0A
P0B0
FLG
0.71H.0
R/W
Bit 0 of port 0B
P0B1
FLG
0.71H.1
R/W
Bit 1 of port 0B
P0B2
FLG
0.71H.2
R/W
Bit 2 of port 0B
P0B3
FLG
0.71H.3
R/W
Bit 3 of port 0B
P0C0
FLG
0.72H.0
R/W
Bit 0 of port 0C
P0C1
FLG
0.72H.1
R/W
Bit 1 of port 0C
P0C2
FLG
0.72H.2
R/W
Bit 2 of port 0C
P0C3
FLG
0.72H.3
R/W
Bit 3 of port 0C
P0D0
FLG
0.73H.0
R/W
Bit 0 of port 0D
P0D1
FLG
0.73H.1
R/W
Bit 1 of port 0D
P0D2
FLG
0.73H.2
R/W
Bit 2 of port 0D
P0D3
FLG
0.73H.3
R/W
Bit 3 of port 0D
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