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參數(shù)資料
| 型號： | UPD17240MC-XXX-5A4-A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO30 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-30 |
| 文件頁數(shù)： | 28/102頁 |
| 文件大小： | 668K |
| 代理商： | UPD17240MC-XXX-5A4-A |
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31
Data Sheet U15002EJ1V0DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.5
Register File (RF)
The register file mainly consists of registers that set the conditions of the peripheral hardware.
These registers can be controlled by the dedicated instructions PEEK and POKE, and the embedded macro
instructions of RA17K, SETn, CLRn, and INITFLG.
2.5.1
Configuration of register file
Figure 2-10 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE
instructions.
The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers
are assigned to addresses 00H to 3FH regardless of the bank, the addresses 00H to 3FH of the general-purpose data
memory cannot be accessed when the PEEK or POKE instruction is used.
The addresses that can be accessed by the PEEK and POKE instructions are addresses 00H to 3FH of the control
registers and 40H to 7FH of the general-purpose data memory. The register file consists of these addresses.
The control registers are assigned to addresses 80H to BFH on the IE-17K to facilitate debugging.
Figure 2-10. Register File Configuration and Register File Access with PEEK or POKE Instructions
0123456789
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Column address
Row
address
Data memory
System register
0
1
2
3
PEEK WR, SP
POKE LCDMD, WR
POKE M063, WR
Control register
Register file
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