參數(shù)資料
型號： UPD17240MC-XXX-5A4-A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO30
封裝： 0.300 INCH, PLASTIC, SSOP-30
文件頁數(shù)： 71/102頁
文件大小： 668K
代理商： UPD17240MC-XXX-5A4-A
70
Data Sheet U15002EJ1V0DS
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
9.3
STOP Mode
In the STOP mode, the system clock (fX) oscillation is stopped and the program execution is stopped to minimize
current consumption.
To set the STOP mode, use the STOP instruction.
The STOP mode release condition can be specified by the STOP instruction operand, as shown in Table 9-4.
After the STOP mode has released, the
PD17246 performs the following.
<1> Resets IRQTM.
<2> Starts the basic interval timer and watchdog timer (does not reset).
<3> Resets and starts the 8-bit timer.
<4> Executes the instruction next to [STOP 8H] when the current value of the 8-bit counter matches the value
of the modulo register (IRQTM is set).
The
PD17246 oscillator is stopped when the STOP instruction has been executed (i.e., in the STOP mode).
Oscillation is not resumed until the STOP mode is released. After the STOP mode has been released, the HALT mode
is set. Set the time required to release the HALT mode by using the timer with modulo function.
The time that elapses from when the STOP mode has been released by occurrence of an interrupt until an operation
mode is set is shown in the following table.
Caution Do not execute an instruction that clears the interrupt request flag (IRQ
×××) for which the
interrupt enable flag (IP
×××) is set immediately before the STOP 8H instruction; otherwise, the
STOP mode may not be set.
8-Bit Modulo Register Set Value
Time Required to Set Operation Mode
(TMM)
After STOP Mode Release
At 4 MHz
40H
4.160 ms (64
s × 65)
FFH
16.384 ms (64
s × 256)
Caution To set the time required for an operation mode to be set after the STOP mode has been released,
make sure that sufficient time is allowed for oscillation to stabilize.
Remark
Set the 8-bit modulo timer before executing STOP instruction.
Table 9-4.
STOP Mode Release Conditions
Operand Value
Release Conditions
1000B (08H)
<1> When any of P0A0 to P0A3 pins goes low
<2> When P0B0 to P0B3, P0C0 to P0C3, and P0D0 to P0D3 are used as input pins and any of these
goes low
<3> If the interrupt request (IRQ) of an interrupt for which the INT pin interrupt enable flag (IP) is set
is generated at the rising or falling edge of the INT pin
<4> If P0E0 to P0E3 are used as input pins when a key matrix is used and if any of these pins goes
low
<5> If P1A0 to P1A2 and P1B0 are used as input pins when a key matrix is used and if the level of any
of these pins is the set clear levelNote
Other than above
Setting prohibited
Note
Set the clear level by using bits 0 to 2 (P1AHL0 to P1AHL2) of the register file at address 05H, and bit 2
(P1BHL0) at address 15H.
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