參數(shù)資料
型號: UPC1862
廠商: NEC Corp.
英文描述: BURST LOCK CLOCK GENERATOR
中文描述: 爆破鎖時鐘發(fā)生器
文件頁數(shù): 28/32頁
文件大小: 252K
代理商: UPC1862
28
μ
PC1862
Care Point for Planning of Application Circuit
1.
Processing of V
CC
pin
Please isolate Chroma. V
CC
from Sync. V
CC
as follows. If you have external processing block of digital signal, don’t
directly supply of the block’s V
DD
.
2.
Application of no using Chroma pin
If you don’t use Chroma pin but use Sync pin on
μ
PC1862, you process pin 1 to pin 18 as follows.
3.
Application of no using Sync pin
If you don’t use Sync pin but use Chroma pin on
μ
PC1862, you process pin 19 to pin 36 as follows. In this case, you
need to input a pin 24 with burst gate pulse from external.
In this application, you can’t use output of pin 20 to pin 23.
Processing IC of
digital signal, etc
V
DD
SGND
Sync (Pin 19 to pin 36)
PC1862
Chroma (Pin 1 to pin 18)
5 V
SV
CC
GND
CGND
10
CV
CC1
2
CV
CC2
14
CV
CC3
15
0.01 F
47 F
0.01 F
0.01 F 47 F
30
25
μ
5 V
TINT
3
CV
CC1
2
CV
CC3
15
CV
CC2
14
0.01
F
47 F
0.01 F
SCO
1
CIN
4
CKO
6
ACCF
5
CKF
7
8
9
10
11
12
13
16
17
18
COUT APCF
CGND
SCOF1 SCOF2SCOF3
VCOO DIVS ESCI
PC1862
μ
5 V
HSOF2
SV
CC
3.3 k
25
3.3 k
5 V
0 V
2.2 k
29
Open
(Don’t use)
Burst Gate Input
Video signal
input
Comp Sync Output
Open
SSI
CSO VSSI HDF
36
35
33
34
32
31
HKO
30
28
27
26
24
23
22
21
FIO
20
VSO
19
N/P
HDO
SGND
HSOF1
HSOF3
AFCF
BGPENHSO CPO
PC1862
μ
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