參數(shù)資料
型號: UPC1862
廠商: NEC Corp.
英文描述: BURST LOCK CLOCK GENERATOR
中文描述: 爆破鎖時鐘發(fā)生器
文件頁數(shù): 22/32頁
文件大小: 252K
代理商: UPC1862
22
μ
PC1862
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Burst gate input
Threshold level 2
V
BGPE2
Burst gate pulse input voltage when Clamp
voltage begins High level is gradually
increased from V
BGPE1
without signal input
3.8
4.0
4.2
V
Vertical free-running
frequency 1
f
V1 (50)
Frequency ratio of HD output to VD output
H sync input: No signal
Pin 33 input: V
CC
V sync input: V
CC
-
f
H
/352
-
Hz
f
V1 (60)
-
f
H
/288
-
Hz
Vertical free-running
f
V2 (50)
Same as f
V1
with the following exception
-
f
H
/288
-
Hz
frequency 2
f
V2 (60)
V sync input: GND
-
f
H
/240
-
Hz
Vertical free-running
f
V3 (50)
Same as f
V1
with the following exception
-
f
H
/368
-
Hz
frequency 3
f
V3 (60)
Pin 33 input: GND
-
f
H
/296
-
Hz
Vertical free-running
frequency 4
f
V4 (50)
Same as f
V1
with the following exception
Pin 33 input: GND
V sync input: GND
-
f
H
/272
-
Hz
f
V4 (60)
-
f
H
/232
-
Hz
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