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參數(shù)資料
| 型號： | UPC1854AGT |
| 廠商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C總線兼容美國的多邊貿易體制處理LSI |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 251K |
| 代理商： | UPC1854AGT |
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μ
PC1854A
24
Data Sheet S12816EJ3V0DS00
(4) Separation setting (write register, subaddresses 03H and 04H, bits D5 to D0)
<1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<2> Write “20H” to bits D5 to D0 (High-band separation setting bits) of subaddress 04H.
<3> Input composite signal to COM pin (300 Hz, 30% modulation, L-only, with noise reduction), and set bits
D5 to D0 (Low-band separation setting bits) of subaddress 03H so that the output level of the ROT pin is
as small as possible.
<4> Change the modulation frequency of the composite signal to 3 kHz, and set bits D5 to D0 of subaddress
04H so that the output level of the ROT pin is as small as possible.
<5> While bits D5 to D0 of subaddress 04H are set as in step <4> above, repeat the setting procedure of step
<3> for bits D5 to D0 of subaddress 03H.
(5) SAP VCO setting (write register, subaddress 05H, bits D6 to D0)
Perform this adjustment with no signal applied.
<1> Add a 1 M
resistor between the SOA pin and GND.
<2> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<3> Write “1” to bit D6 (5 f
H
monitor: ON) of subaddress 05H.
<4> Connect a frequency counter to the ROT pin, and set bits D5 to D0 of subaddress 05H (SAP VCO setting
bits) so that 78.67 kHz (
±
0.5 kHz) is displayed on the frequency counter.
<5> When setting is completed, write “0” to bit D6 (5 f
H
monitor: OFF) of subaddress 05H.
<6> Delete the 1 M
resistor between the SOA pin and GND.
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