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參數(shù)資料
| 型號： | UPC1854AGT |
| 廠商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C總線兼容美國的多邊貿(mào)易體制處理LSI |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 251K |
| 代理商： | UPC1854AGT |
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μ
PC1854A
20
Data Sheet S12816EJ3V0DS00
3.2 Data Transfer Format
An example of data transfer in the write mode is shown in Figure 3-4.
Figure 3-4. Data Transfer Example in Write Mode
Data consists of 8-bit units. This 8-bit data must always be followed by an acknowledge bit. Data transfer must
be done on an MSB-first basis.
The first byte after a start condition specifies the slave address. The slave address consists of 7 bits.
Table 3-1 shows the slave addresses of the
μ
PC1854A. These slave addresses are registered by Philips.
Table 3-1. Slave Addresses of
μ
PC1854A
Slave address
D6
D5
D4
D3
D2
D1
D0
Read/Write
Mode
Write
1
0
0
0
1
1
1
0
Read
1
0
0
0
1
1
1
1
The bit following the slave address is the read/write bit specifying the direction of the data to be transferred.
During the read operation, data is transferred from the
μ
PC1854A to the master CPU. During the write opera-
tion, data is transferred from the master CPU to the
μ
PC1854A. “0” and “1” are written to the Read/Write bit during
the Write and Read modes, respectively.
The byte following the slave address is the subaddress of the
μ
PC1854A in the write mode.
The
μ
PC1854A has seven subaddresses, SA
0
to SA
6
, which are made up of 8 bits. Following the subaddress
byte is the data to be set to the subaddress.
Start
Slave address
Subaddress
Read/
Write Acknowledge
Acknow-
ledge
Acknow-
ledge
data
Stop
D6
SDA
SCL
D5 D4 D3 D2 D1 D0mode
D6 D5
D7
D4 D3 D2 D1 D0
D6 D5
D7
D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
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