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參數(shù)資料
| 型號： | UPC1854AGT |
| 廠商： | NEC Corp. |
| 英文描述： | I2C BUS-COMPATIBLE US MTS PROCESSING LSI |
| 中文描述： | I2C總線兼容美國的多邊貿(mào)易體制處理LSI |
| 文件頁數(shù)： | 21/48頁 |
| 文件大?。?/td> | 251K |
| 代理商： | UPC1854AGT |
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μ
PC1854A
21
Data Sheet S12816EJ3V0DS00
(1) 1-byte data transfer
The format for 1-byte data transfer is the following:
(2) Continuous data transfer
The format when transferring multiple (7) bytes of data at one time is the following:
The master CPU transfers “00H” as subaddress SA0 following the start condition and slave address. After the
subaddress SA
0
, the master CPU transfers the SA0 data, and continues with SA
1
, SA2, ..., SA
6
data without
transferring stop conditions in between.
The subaddress is automatically incremented. Finally, the stop condition is transferred and the transfer is
completed.
(3) Data read
The
μ
PC1854A has one read register. The contents of this register can be read by the master CPU.
The format when data is read is the following:
(4) Acknowledge
In the case of the I
2
C bus, an acknowledge bit is added to the data as the 9th bit to determine whether data
transfer was successful. The master determines the success or failure of data transfer based on whether this
acknowledge bit is a logical low or high.
If the acknowledge interval is a logical low, this indicates that data transfer was successful. If it is a logical
high, this indicates that data transfer was unsuccessful or that the slave side forcibly released the bus as a
non-acknowledge state.
Start
Slave
address
Write
mode
Acknow
-ledge
Subaddress
Acknow
-ledge
Data
Acknow
-ledge
Stop
Start
Slave
address
Write
mode
Acknow
-ledge
Subaddress
Acknow
-ledge
Data1
Acknow
-ledge
Data2
Acknow
-ledge
Acknow
-ledge
Stop
Data7
Start
Slave
address
Acknow
-ledge
Data
Non-
acknow
-ledge
Stop
Read
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