參數(shù)資料
型號: UDA1384H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Multichannel audio coder-decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 46/55頁
文件大?。?/td> 276K
代理商: UDA1384H
9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
46 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
[1]
The system clock should not exceed 58 MHz in any mode.
[2]
The bit clock frequency should not exceed 256 times the corresponding sampling frequency.
[3]
C
b
is the total capacitance for each bus line.
To be suppressed by the input filter.
[4]
t
dis(L3)R
L3DATA disable time for read
data
0
-
50
ns
I
2
C-bus interface timing (see
Figure 20
)
SCL timing
f
SCL
SCL clock frequency
t
LOW
SCL LOW time
t
HIGH
SCL HIGH time
t
r
rise time SDA and SCL
t
f
fall time SDA and SCL
SDA timing
t
BUF
bus free time between STOP
and START condition
t
SU;STA
set-up time repeated START
t
HD;STA
hold time START condition
t
SU;DAT
data set-up time
t
HD;DAT
data hold time
t
SU;STO
set-up time STOP condition
t
SP
pulse width of spikes
C
b
capacitive load for each bus
line
0
1.3
0.6
-
-
-
400
-
-
300
300
kHz
μ
s
μ
s
ns
ns
[3]
20 + 0.1C
b
-
[3]
20 + 0.1C
b
-
1.3
-
-
μ
s
0.6
0.6
100
0
0.6
-
-
-
-
-
-
-
-
-
-
-
-
50
400
μ
s
μ
s
ns
μ
s
μ
s
ns
pF
[4]
0
-
Table 67:
V
DDD
= V
DDA(AD)
= V
DDA(AD)
= 2.7 V to 3.6 V; T
amb
=
20
°
C to +85
°
C; typical timing specified at sampling frequency
f
s
= 48 kHz; unless otherwise specified.
Symbol
Parameter
Conditions
Timing
…continued
Min
Typ
Max
Unit
Fig 16. System clock timing
mgr984
T
sys
t
CWH
t
CWL
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