參數(shù)資料
型號(hào): UDA1380TT
元件分類: 通用總線功能
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁數(shù): 56/68頁
文件大?。?/td> 278K
代理商: UDA1380TT
2002 Sep 16
56
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
18 TIMING
V
DDD
= V
DDA(AD)
= V
DDA(DA)
= V
DDA(HP)
= 2.7 to 3.6 V; T
amb
=
20 to +85
°
C; all voltages referenced to ground; unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
System clock timing;
note 1
T
sys
system clock cycle time
f
sys
= 256f
s
f
sys
= 384f
s
f
sys
= 512f
s
f
sys
= 768f
s
f
sys
< 19.2 MHz
f
sys
19.2 MHz
f
sys
< 19.2 MHz
f
sys
19.2 MHz
35
23
17
17
0.3T
sys
0.4T
sys
0.3T
sys
0.4T
sys
81
54
41
27
250
170
130
90
0.7T
sys
0.6T
sys
0.7T
sys
0.6T
sys
ns
ns
ns
ns
ns
ns
ns
ns
t
CWL
system clock LOW time
t
CWH
system clock HIGH time
Serial interface input/output data timing
(see Fig.17)
f
BCK
T
cy(BCK)
t
BCKH
t
BCKL
t
r
t
f
t
su(WS)
t
h(WS)
t
su(DATAI)
t
h(DATAI)
t
h(DATAO)
t
d(DATAO-BCK)
t
d(DATAO-WS)
L3-bus interface timing
(see Figures 18 and 19)
bit clock frequency
bit clock cycle time
bit clock HIGH time
bit clock LOW time
rise time
fall time
word select set-up time
word select hold time
data input set-up time
data input hold time
data output hold time
data output to bit clock delay
data output to word select delay
30
30
10
10
10
10
0
128f
s
1
128
T
cy(s)(2)
s
20
20
30
30
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
r
t
f
T
cy(CLK)L3
t
CLK(L3)H
t
CLK(L3)L
t
su(L3)A
rise time
fall time
L3CLOCK cycle time
L3CLOCK HIGH time
L3CLOCK LOW time
L3MODE set-up time in address
mode
L3MODE hold time in address
mode
L3MODE set-up time in data
transfer mode
L3MODE hold time in data transfer
mode
note 3
note 3
note 4
note 4
note 4
500
250
250
190
10
10
ns/V
ns/V
ns
ns
ns
ns
t
h(L3)A
190
ns
t
su(L3)D
190
ns
t
h(L3)D
190
ns
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