參數(shù)資料
型號(hào): UDA1380TT
元件分類(lèi): 通用總線(xiàn)功能
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁(yè)數(shù): 26/68頁(yè)
文件大?。?/td> 278K
代理商: UDA1380TT
2002 Sep 16
26
Philips Semiconductors
Product specification
Stereo audio coder-decoder
for MD, CD and MP3
UDA1380
10 I
2
C-BUS INTERFACE DESCRIPTION
The UDA1380 supports I
2
C-bus microcontroller interface
mode as well as the L3-bus mode; all features can be
controlled by the microcontroller with the same register
addresses as in the L3-bus mode.
The exchange of data and control information between the
microcontroller and the UDA1380 in I
2
C-bus mode is
accomplished through a serial hardware interface
comprising the following pins:
L3CLOCK/SCL: microcontroller interface clock line,
SCL
L3MODE: sets the bit A1of the I
2
C-bus device address
L3DATA/SDA: microcontroller interface data line, SDA.
Figure 20 shows the clock and data timing of the I
2
C-bus
transfer.
10.1
Addressing
Before any data is transmitted on the I
2
C-bus, the device
whichshouldrespondisaddressedfirst.Theaddressingis
always done with the first byte transmitted after the start
procedure. The UDA1380 device address is
[A6 to A0] 00110(A1)0, with bit A1 as the address
selection bit (two addresses possible).
10.1.1
D
EVICE ADDRESS
(
PIN
A1)
The UDA1380 acts as either a slave receiver or a slave
transmitter. Therefore the clock signal SCL is only an input
signal. The data signal SDA is a bidirectional line. Table 11
shows the device address of the UDA1380.
The device can be set to one of the two addresses by
using bit A1 (which is pin L3MODE) to select.
Table 11
I
2
C-bus device address
10.1.2
R
EGISTER ADDRESS
Table 12 shows the register address format of the
UDA1380. The register mapping in I
2
C-bus mode is the
same as for the L3-bus interface.
Table 12
I
2
C-bus register address
(MSB)
BIT
(LSB)
0
0
1
1
0
A1
0
R/W
(MSB)
BIT
(LSB)
0
A6
A5
A4
A3
A2
A1
A0
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