參數(shù)資料
型號： TVP70025IPZP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： GREEN, PLASTIC, HTQFP-100
文件頁數(shù)： 6/59頁
文件大?。?/td> 519K
代理商： TVP70025IPZP
COAST
HSYNC
Phase
Detector
PLL Control
Register 03h
Bit [5:3]
PLL Control
Register 03h
Bit [7:6]
Phase Select
Register 04h
Bit [7:3]
Charge
Pump
VCO
Phase
Select
Divider
ADC
Sampling
CLK
External
Clock
PLL Divide
Register 01h and 02h
1:0]
Bit [1
Loop
Filter
N = 1 or 2
Post
Divider
÷N
Post Divider
Register 04h
Bit [0]
SLES232B
– JUNE 2008 – REVISED MAY 2011
Automatic Level Control (ALC)
The ALC circuit maintains the level of the signal to be set at a value that is programmed at the fine offset I2C
register. It consists of a pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by
the I2C register at subaddress 26h.
The ALC circuit needs a timing pulse generated internally but the user should program the position properly. The
ALC pulse must be positioned after the clamp pulse. The position of ALC pulse is controlled by ALC placement
I2C register at address 31h. This is available only for internal ALC pulse timing. When using an external clamp
pulse, the fine clamp and the ALC both start on the leading edge of the external clamp pulse. Therefore, it is
recommended to keep the external clamp pulse as long as possible.
Analog-to-Digital Converters (ADCs)
All ADCs have a resolution of 10 bits and can operate up to 90 MSPS. All A/D channels receive an identical
clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 90 MHz. All ADC reference
voltages are generated internally. The external sampling clock also can be used.
Horizontal PLL
The horizontal PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to
derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal
sync signal supplied on the HSYNC input or from extracted horizontal sync of the sync slicer block for embedded
sync signals. The horizontal PLL consists of a phase detector, charge pump, loop filter, voltage controlled
oscillator (VCO), phase select, feedback divider, and post divider. The horizontal PLL block diagram is shown in
Figure 3. Horizontal PLL Block Diagram
The COAST signal is used to allow the H-PLL to keep running at the same frequency, in the absence of the
incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other
time that the HSYNC is not available. The fine clamp is disabled during the H-PLL coast interval.
There are several PLL controls to produce the correct sampling clock. The 12-bit feedback divider register is
programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to
90 MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-pass
loop filter. The applicable current values are listed in Table 5.
14
Copyright
2008–2011, Texas Instruments Incorporated
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