參數(shù)資料
型號: TVP70025IPZP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: GREEN, PLASTIC, HTQFP-100
文件頁數(shù): 14/59頁
文件大?。?/td> 519K
代理商: TVP70025IPZP
SLES232B
– JUNE 2008 – REVISED MAY 2011
Embedded Syncs
Standard embedded syncs insert SAV and EAV codes into the data stream on the rising and falling edges of
AVID. These codes contain the V and F bits that also define vertical timing. Table 7 gives the format of the SAV
and EAV codes.
H = 1 always indicates EAV. H = 0 always indicates SAV. The alignment of V and F to the line and field counter
varies depending on the standard. The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 7. EAV and SAV Sequence
Y9 (MSB)
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Preamble
1
Preamble
0
Preamble
0
Status
1
F
V
H
P3
P2
P1
P0
0
The pixel locations where SAV/EAV embedded sync codes are inserted can be programmed using the AVID
Start Pixel and AVID Stop Pixel I2C registers. The AVID start location is determined from the HSYNC interval,
horizontal back porch interval (Hbp) and a digital process delay factor (PDELAY) required for compensation of
internal TVP70025I delays. An additional 4 bytes must be added to the active pixel interval between AVID start
and AVID stop to accommodate embedded sync insertion.
AVID Start Pixel = PDELAY + HSYNC + Hbp
AVID Stop Pixel = AVID Start Pixel + Active Pixels + 4
NOTE
Some AVID Stop Pixel calculations will exceed the HPLL-Feedback Register setting, or
total pixels per line. When this occurs, subtract total pixels per line from AVID Stop Pixel.
NOTE
PDELAY is typically 27 pixels but may vary slightly depending on other TVP70025I settings
such as the Sync-on-Green Threshold setting (I2C register 10h) and the SOG LPF setting
(I2C register 1Ah).
The line numbers where the embedded V-bit and F-bit occur are controlled by I2C registers 44h through 49h,
which define the vertical blanking interval and field start positions. See Table 8 for typical embedded syncs
settings.
Table 8. Typical Embedded Sync Settings
VBLK
F-bit
Output
AVID Start Pixel
AVID Stop Pixel
Field 0
Field 1
Field 0
Field 1
Field 0
Field 1
Format
Start Line
Durationt
Duration
Start Line
Input Format
Register
15h
41h
40h
43h
42h
44h
45h
46h
47h
48h
49h
480i60Hz
47h
00h
95h
00h
0Fh
01h
13h
02h
01h
480p60Hz
47h
00h
93h
00h
0Dh
09h
2Dh
00h
720p60Hz
47h
01h
47h
06h
4Bh
05h
1Eh
00h
1080i60Hz
47h
01h
07h
08h
8Bh
02h
16h
17h
00h
Copyright
2008–2011, Texas Instruments Incorporated
21
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