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參數(shù)資料
| 型號： | TVP5160PNPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | PLASTIC, HTQFP-128 |
| 文件頁數(shù)： | 30/119頁 |
| 文件大?。?/td> | 1347K |
| 代理商： | TVP5160PNPG4 |
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Introduction
8
February 2005 Revised April 2006
SLES135A
Table 21. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
I/O
DESCRIPTION
Analog Video
VI_1
VI_2
VI_3
VI_4
VI_5
VI_6
VI_7
VI_8
VI_9
VI_10
VI_11
VI_12
3
4
5
7
8
9
17
18
19
21
22
23
I
VI_x: analog video inputs
Up to 12 composite, 6 S-Video, or 3 component video inputs (or combinations thereof) can be
supported. Also, 4-channel SCART is supported.
The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 F.
The possible input configurations are listed in the input select register 00h.
Unused inputs must be connected to ground through 0.1-F capacitors.
Analog_out
127
O
Unbuffered analog video output
Clock Signals
XIN
121
I
External clock reference input. It may connected to external oscillator with 1.8-V compatible clock
signal or 14.31818-MHz crystal oscillator.
XOUT
122
O
External clock reference output. Not connected if XTAL1 is driven by an external single-ended
oscillator.
SCLK
84
O
Line-locked data output clock
Digital Video
Y[9:0]
8791,
9498
O
Digital video output of Y/YCbCr, Y_9 is MSB and Y_0 is LSB. For 8-bit operation, the upper 8 bits
must be connected.
C[9:0] / GPIO
FSO
DB
DG
DR
101104,
107110,
113, 114
101
102
103
104
I/O
I
Digital video output of CbCr, C_9 is MSB and C_0 is LSB. These terminals can be programmable
general purpose I/O, or as digital overlay controls. For 8-bit operation, the upper 8 bits must be
connected.
Fast-switch overlay between digital RGB and any video input
Digital BLUE input from overlay device
Digital GREEN input from overlay device
Digital RED input from overlay device
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
Miscellaneous Signals
RESETB
36
I
Reset input, active low
PWDN
35
I
Power down input
1 = Power down
0 = Normal mode
GLCO / GPIO /
I2CA0
83
I/O
Genlock control output (GLCO). Supports the real-time control (RTC) format. This pin can also be
configured as a general-purpose I/O (GPIO).
During power on reset this pin is sampled along with pin 82 (I2CA1) as an input to determine the I2C
address the device will be configured to. A 10-k resistor pulls this either high (to IOVDD) or low to
select between addresses.
GPIO / I2CA1
82
I/O
Programmable general purpose I/O
During power on reset this pin is sampled along with pin 83 (I2CA0) as an input to determine the I2C
address the device will be configured to. A 10-k resistor pulls this either high (to IOVDD) or low to
select between addresses.
INTREQ
32
O
Interrupt request output (open drain when programmed to be active low)
FSS
119
I
SCART fast switch input
NC
6, 10, 20,
24
N/A No internal connection. Connect to AGND through 0.1-F capacitors for future compatibility.
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