參數(shù)資料
型號: TVP5160PNPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉換
英文描述: COLOR SIGNAL DECODER, PQFP128
封裝: PLASTIC, HTQFP-128
文件頁數(shù): 103/119頁
文件大?。?/td> 1347K
代理商: TVP5160PNPG4
Internal Control Registers
74
February 2005 Revised April 2006
SLES135A
4.1.101 3DYC PAL VCR Threshold
Subaddress
99h
Default
20h
7
6
5
4
3
2
1
0
Thresh [7:0]
This register controls how 3DYC is enabled/disabled for VCR modes.
4.1.102 Vertical Line Count
Subaddress
9Ah9Bh
Read only
Subaddress
7
6
5
4
3
2
1
0
9Ah
Vertical line [7:0]
9Bh
Reserved
Vertical line[9:8]
Vertical line [9:0] represent the detected a total number of lines from the previous frame. This can be used with
nonstandard video signals such as a VCR in trick mode to synchronize downstream video circuitry.
Since this register is a double-byte register it is necessary to capture the setting into the register to ensure that
the value is not updated between reading the lower and upper bytes. In order to cause this register to capture
the current settings bit 0 of I2C register 97h (status request) must be set to a 1b. Once the internal processor
has updated this register, bit 0 of register 97h is cleared, indicating that both bytes of the vertical line count
register have been updated and can be read. Either byte may be read first since no further update will occur
until bit 0 of 97h is set to 1b again.
4.1.103 AGC Decrement Delay
Subaddress
9Eh
Default
1Eh
7
6
5
4
3
2
1
0
AGC decrement delay [7:0]
AGC decrement delay: Number of frames to delay gain decrements
1111 1111 = 255
L
0001 1110 = 30 (default)
L
0000 0000 = 0
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TVP5160PNP COLOR SIGNAL DECODER, PQFP128
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