參數(shù)資料
型號： TVP5160PNPG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： PLASTIC, HTQFP-128
文件頁數(shù)： 117/119頁
文件大?。?/td> 1347K
代理商： TVP5160PNPG4
Internal Control Registers
87
February 2005 Revised April 2006
SLES135A
4.1.128 Interrupt Clear 0
Subaddress
F6h
Default
00h
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS
VPS/EPG
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed clear
0 = No effect (default)
1 = Clear FIFO_THRES bit in status register 0 bit 7
TTX: Teletext data available clear
0 = No effect (default)
1 = Clear TTX available bit in status register 0 bit 6
WSS: WSS data available clear
0 = No effect (default)
1 = Clear WSS available bit in status register 0 bit 5
VPS/EPG: VPS/EPG data available clear
0 = No effect (default)
1 = Clear VPS available bit in status register 0 bit 4
VITC: VITC data available clear
0 = Disabled (default)
1 = Clear VITC available bit in status register 0 bit 3
CC F2: CC field 2 data available clear
0 = Disabled (default)
1 = Clear CC field 2 available bit in status register 0 bit 2
CC F1: CC field 1 data available clear
0 = Disabled (default)
1 = Clear CC field 1 available bit in status register 0 bit 1
LINE: Line number interrupt clear
0 = Disabled (default)
1 = Clear Line interrupt available bit in status register 0 bit 0
The host interrupt clear 0 and 1 registers are used by the external processor to clear the interrupt status bits
in the host interrupt status 0 and 1 registers. When no nonmasked interrupts remain set in the registers, the
external interrupt pin will also become inactive.
4.1.129 Interrupt Clear 1
Subaddress
F7h
Default
00h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full: Clear FIFO full flag
0 = No effect (default)
1 = Clear bit 0 (FIFO full flag) in the interrupt status 1 register at subaddress F3h and the interrupt raw
status 1 register at subaddress F1h
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PDF描述
TVP5160PNP COLOR SIGNAL DECODER, PQFP128
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