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參數(shù)資料
| 型號： | TUA6100B6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Components for Satellite Receiver Units |
| 中文描述： | 元件衛(wèi)星接收單元 |
| 文件頁數(shù)： | 23/46頁 |
| 文件大?。?/td> | 819K |
| 代理商： | TUA6100B6 |
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Preliminary Specification
TUA6100B6
High-Frequency-Products
18
26.1.01
Control-Register
(Register 00) ---> Subaddress 00H
Bit
0
Normal-Mode
1
Test-Mode
D7 must be = 1 (Test-Mode)
R-counter / 2 -> output to Port P0
N-counter / 2 -> output to Port P1
Port P0 -> input to R-counter
Port P1 -> input to N-counter
D7 must be = 0 (Normal-Mode)
0
Bit D5 not active
1
Bit D5 active
D5 is only active for D6 = 1, D7 = 0
0
LockDetect output on Port 0
1
LockDetect output on Port 2
0
PhaseDetector polarity negative
Test-Mode:
It is possible to switch into an internal chip test mode
by bit D7 of the control register (subaddress 00H).
If test mode is activated there are two test options
available by bit D6 of the control register:
D6 = 0 --> Test-Mode1:
In this case the output frequencies of the
counters divided by 2 ( ! ) are put out to the
Ports P0 ( R-counter output frequency / 2 )
and P1 ( N-counter output frequency / 2 )
Nevertheless the phase detector and the
charge pump are in function
( lock detector = OFF ).
D6 = 1 --> Test-Mode2:
In this case the phase detector, charge pump
and lock detector (= ON) can be tested by
external frequencies which are applied to the
Ports P0 (path of the R-counter frequency)
and P1 (path of the N-counter frequency).
( Note: LD_out only on port P2 visible! )
Function
MSB
D7
D6
0
1
D5
D4
1
PhaseDetector polarity positive
D3
D2
D3 D2 Synthesizer ChargePump current
0
0
100μA
0
1
500μA
1
0
1mA
1
1
2mA
0
Synthesizer ChargePump disabled
1
Synthesizer ChargePump enabled
0
Synthesizer Loopfilter OP disabled
1
Synthesizer Loopfilter OP enabled
Status-Register (READ)
(Register 128) ---> Subaddress 80H
Bit
Function
MSB
D7
0
1
1
1
synthesizer PLL unlocked
synthesizer PLL locked
D1
D6
.....
for future use, all bits = 1
D0
LSB
D0
LSB
1
Prescaler, Ports, GHz-PLL
(Register 01) ---> Subaddress 01H
Bit
0
GHz VCO = 3.4-6.2 GHz
1
GHz VCO = 6-8.6 GHz
0
Prescaler divide ratio 32/33
1
Prescaler divide ratio 64/65
D21
D20
N-Counter GHz-PLL
0
0
0
1
1
0
1
1
0
Port_1 output = low level
1
Port_1 output = high level
0
Port_0 output = low level
1
Port_0 output = high level
Ports, GHz-PLL
(Register 02) ---> Subaddress 02H
Bit
Function
Function
MSB
D23
MSB
D15
0
not used (must be=0)
D22
D14
0
1
base band amplifier enabled
base band amplifier disabled
R-Counter GHz-PLL
D21
D20
D13
D12
D13
0
0
1
1
D12
0
1
0
1
: 3
: 4
: 2
: 3
: 3
: 4
: 2
: 3
D19
D11
0
1
0
1
-
-
Port_2 output = low level
Port_2 output = high level
D18
D10
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