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    參數(shù)資料
    型號: TUA6100B6
    廠商: INFINEON TECHNOLOGIES AG
    英文描述: Components for Satellite Receiver Units
    中文描述: 元件衛(wèi)星接收單元
    文件頁數(shù): 22/46頁
    文件大?。?/td> 819K
    代理商: TUA6100B6
    Preliminary Specification
    TUA6100B6
    High-Frequency-Products
    17
    26.1.01
    8.13.4 Data Byte Specification
    Register 00
    Subaddress 00H
    Control - Register
    Bit
    Function
    MSB
    D7
    Normal-Mode
    Test-Modes (in/out)
    LockDetect (on/off)
    LockDetect-Out
    on Port 0 / 2
    Phase Detector
    polarity (+/-)
    D3
    ChargePump current
    100/500μA ,1/2mA
    D2
    Charge Pump
    (on/off)
    D0
    LSB
    (on/off)
    Register 01
    Subaddress 01H
    A/N-Counter,Ports,VCO
    Bit
    Function
    MSB
    D23
    Prescaler Switch
    32/33 <--> 64/65
    Register 02
    Subaddress 02H
    R-Counter,Ports,VCO
    Bit
    Function
    MSB
    D15
    (must be=0)
    Base band
    amplifier disable
    Register 03
    Subaddress 03H
    for future use
    Bit
    Function
    MSB
    D7
    Test-Mode /
    GHz VCO Switch
    not used
    -
    D6
    D22
    D14
    D6
    -
    D5
    D21
    N1
    2
    N-Counter
    GHz-PLL
    D13
    R1
    2
    R-Counter
    GHz-PLL
    D5
    -
    D4
    D20
    N0
    2
    D12
    R0
    2
    D4
    -
    D19
    D18
    Port 1
    Port 0
    2
    1
    0
    D11
    D10
    not used
    Port 2
    D3
    D2
    -
    -
    D1
    D17
    divide
    ratio of the
    synthesizer
    N-Counter
    2 ....2047
    D9
    2
    9
    divide
    ratio of the
    synthesizer
    R-Counter
    2 ....1023
    D1
    -
    Loop filter OP
    D16
    2
    9
    D8
    2
    8
    D0
    LSB
    -
    D15
    D14
    D13
    D12
    D11
    D10
    D9
    2
    8
    2
    7
    2
    6
    2
    5
    2
    4
    2
    3
    2
    2
    D7
    D6
    D5
    D4
    D3
    D2
    D1
    D0
    LSB
    2
    7
    2
    6
    2
    5
    2
    4
    2
    3
    2
    2
    2
    1
    Register 80
    Subaddress 80H
    Status - Register (READ)
    Bit
    Function
    D8
    2
    1
    2
    0
    MSB
    D7
    D6
    D5
    D4
    D3
    D2
    D1
    D0
    LSB
    LockDetect-Out
    D7
    2
    0
    for future use
    all bits high
    D6
    D5
    D4
    D3
    D2
    D1
    D0
    LSB
    2
    6
    2
    5
    2
    4
    2
    3
    2
    2
    2
    1
    divide
    ratio of the
    synthesizer
    A-Counter
    0 ....127
    2
    0
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