TSC2003
16
SBAS162A
www.ti.com
Once the master receives the acknowledge bit from the
TSC2003, the master writes the command byte to the slave
(see Figure 11). After the command byte is received by the
slave, the slave issues another acknowledge bit. The master
then ends the Write Cycle by issuing a repeated START or
a STOP condition, as shown in Figure 12.
If the master sends additional command bytes after the initial
byte, before sending a STOP or repeated START condition,
the TSC2003 will not acknowledge those bytes.
The input multiplexer for the A/D converter has its channel
selected when bits C3 through C0 are clocked in. If the selected
channel is an X-,Y-, or Z-position measurement, the appropriate
drivers will turn on once the acquisition period begins.
When R/W = 0, the input sample acquisition period starts on
the falling edge of SCL once the C0 bit of the command byte
has been latched, and ends when a STOP or repeated START
condition has been issued. A/D conversion starts immedi-
ately after the acquisition period. The multiplexer inputs to
the A/D converter are disabled once the conversion period
starts. However, if an X-, Y-, or Z-position is being mea-
sured, the respective touch screen drivers remain on during
the conversion period. A complete Write Cycle is shown in
Figure 12.
SDA
SCL
1
00
10
A1
A0
R/W
0
C3
C2
C1
C0 PD1 PD0
M
X
0
START
ADS7839
ACK
ADS7839
ACK
Address Byte
Command Byte
Acquisition
Conversion
STOP or
REPEATED START
FIGURE 12. Complete I2C Serial Write Transmission.
Read A Conversion/Read Cycle
For best performance, the I2C bus should remain in an idle
state while an A/D conversion is taking place. This prevents
digital clock noise from affecting the bit decisions being made
by the TSC2003. The master should wait for at least 10
s
before attempting to read data from the TSC2003 to realize
this best performance. However, the master does not need to
wait for a completed conversion before beginning a read from
the slave, if full 12-bit performance is not necessary.
Data access begins with the master issuing a START condition
followed by the address byte (see Figure 10) with R/W = 1.
Once the eighth bit has been received, and the address
matches, the slave issues an acknowledge. The first byte of
serial data will follow (D11-D4, MSB first).
After the first byte has been sent by the slave, it releases the
SDA line for the master to issue an acknowledge. The slave
responds with the second byte of serial data upon receiving
the acknowledge from the master (D3-D0, followed by four
0 bits). The second byte is followed by a NOT acknowledge
bit (ACK = 1) from the master to indicate that the last data
byte has been received. If the master acknowledges the
second data byte, then the data will repeat on subsequent
reads with ACKs between bytes. This is true in both 12-bit
and 8-bit mode. The master will then issue a STOP condi-
tion, which ends the Read Cycle, as shown in Figure 13.
SDA
SCL
1
00
10
A1
A0
R/W
1
0
D11
D10
D9
D8
D7
D6
D5
D4
0
D3
D2
D1
D0
00
0
1
START
ADS7839
ACK
MASTER
ACK
MASTER
NACK
STOP or
REPEATED START
Address Byte
Date Byte 1
Date Byte 2
FIGURE 13. Complete I2C Serial Read Transmission.