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| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 98/146頁(yè) |
| 文件大小： | 770K |
| 代理商： | TSB43AA82PGE |
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329
3.4.38.2 DTF Control Register 1 at B4h
BITS
ACRONYM
DIR
DESCRIPTION
031
DTF_BlockCount/
DTF_BlockSize
R/W
DTF transmit block count / DTF transmit block size (bytes). When LongBlk in DMA Control (90h) is set to 1,
it is the DTF_BlockSize. DRFBlockSize specifies the transmitted blocksize value. When LongBlk is set to
0, this value is the DTF_BlockCount. DTF_BlockCount specifies the number of received blocks.
DTF_BlockCount is decremented during transmission automatically. This register defaults to 0 and is set
to 0 on a bus reset.
3.4.38.3 DTF Control Register 2 at B8h
BITS
ACRONYM
DIR
DESCRIPTION
015
DTF_destination_ID
R/W
DTF transferred destination ID. DTF_destination_ID specifies transfer destination ID.
1631
DTF_destination_offset_hi
R/W
DTF transferred destination start offset high. DTF_destination_offset_hi specifies transfer
destination offset high.
3.4.38.4 DTF Control Register 3 at BCh
BITS
ACRONYM
DIR
DESCRIPTION
031
DTF_destination_offset_lo
R/W
DTF transfer destination start offset low. DTF_destination_offset_lo specifies transfer
destination offset low.
3.4.39 DRF Control Registers at C0h, C4h, C8h, and CCh (DRPktz at 90h = 0)—Direct
When DRPktz is set to 0, the DRF control registers describe the direct mode. The direct mode is primarily used with
DPP. These registers default to 0000 0000h and are unaffected by a bus reset.
3.4.39.1 DRF Control Register 0 at C0h
BITS
ACRONYM
DIR
DESCRIPTION
0
DRFBIdEn
R/W
DRF bus ID check enable. Enables bus ID check for received write request routing control.
Note: Valid only when DRFAdrEn = 1.
1
DRFSIdEn
R/W
DRF source ID check enable. Enables source ID check for received write request routing control.
Note: Valid only when DRFAdrEn = 1.
2
DRFAdrEn
R/W
DRF address enable. Enables the routing function for the received write request. In this mode, write
request packets with a destination address specified by the DRF control 0/1/2 addresses are stored in the
DRF.
331
Reserved
N/A
Reserved
C0h (DRFBIdEn, DRFSIdEn, DRFAdrEn)
000
001
010
011
100
101
110
111
All matched packets
ARF
DRF
ARF
DRF
ARF
DRF
ARF
DRF
Unmatched source_ID
ARF
DRF
ARF
DRF
ARF
Unmatched address
ARF
3.4.39.2 DRF Control Register 1 at C4h
BITS
ACRONYM
DIR
DESCRIPTION
031
DRF_destination_Width
R/W
DRF destination width. DRF_destination_Width specifies the address depth of the received write
request packets to the DRF.
3.4.39.3 DRF Control Register 2 at C8h
BITS
ACRONYM
DIR
DESCRIPTION
016
DRF_destination_ID
R/W
DRF destination ID. DRF_destination_ID specifies the transferred destination ID.
1731
DRF_destination_offset_hi
R/W
DRF destination offset high. DRF_destination_offset_hi specifies the transferred destination
offset high.
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