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| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 91/146頁(yè) |
| 文件大小： | 770K |
| 代理商： | TSB43AA82PGE |
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323
3.4.28.3 CRF Data Read Register at 88h
BITS
ACRONYM
DIR
DESCRIPTION
031
CRFRead
R/O
CRF data read access register. This read-only register provides the host with the capability to read a
quadlet of the received packet from the CRF. Each read outputs the next quadlet from the CRF. If the CRF
is empty, the last valid value is read.
3.4.29 Configuration ROM Control Register at 8Ch
This register defaults to 0000 0000h and is unaffected by a bus reset. This register must be quadlet aligned.
BITS
ACRONYM
DIR
DESCRIPTION
05
Reserved
N/A
Reserved
615
AR_CSR_Size
R/W
Autoresponse in configuration ROM size. AR_CSR_Size is equal to the byte size number responded to
automatically in the ConfigROM. AR_CSR_Size must be less than 228h.
1620
Reserved
N/A
Reserved.
2131
CSR_Size
R/W
Configuration ROM Size. CSR_Size is equal to the ConifgROM size number in bytes. CSR_Size must be
less than 400h.
3.4.30 DMA Control Register at 90h
This register defaults to 0029 2440h and, except for the bits specified, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
DMARW
R/W
DMA read/write. This bit controls the DMA input/output (to/from TSB43AA82) mode control for particular
bus mode. When DMARW is set to 1, the DMA bulky interface is used for input. When DMARW is set to 0,
DMA bulky interface is used for output. This bit defaults to 0 and is set to 0 on a bus reset.
1
Reserved
N/A
Reserved
2
DRFEn
R/W
DRF enable. When DRFEn is set to 1, the DRF is enabled to receive data. When DRFEn is set to 0, the
DRF is disabled to receive data.
3
DTFEn
R/W
DTF enable. When DTFEn is set to 1, the DTF is enabled to transmit data. When DTFEn is set to 0, the DTF
is disabled to transmit data. This bit is active only when DTPktz = 0.This bit defaults to 0 and is set to 0 on a
bus reset. NOTE: DTFClr must be set before setting DTFEn. Failure to set DTFClr results in a transmit
error.
4
DRPktz
R/W
DRF packetizer enable. When DRPktz is set to 1, the DRF packetizer is ready to transmit read request
packets. When DRPktz is set to 0, it is not ready to transmit read request packets and the DRF is in DPP
mode.
5
DTPktz
R/W
DTF packetizer enable. When DTPktz is set to 1, the DTF packetizer is ready to transmit write request
packets. When DTPktz is set to 0, it is not ready to transmit write request packets.
6
DRSpDis
R/W
DRF packetizer split transaction disabled. When DRSpDis is set to 0, the DRF packetizer waits for the
response packet if the transaction is acknowledged with an ack_pending.
When DRSpDis is set to 1, the DRF packetizer does not wait for the response packet even if the
transaction is acknowledged with an ack_pending.
7
DTSpDis
R/W
DTF packetizer split transaction disable. When DTSpDis is set to 0, the DTF packetizer waits for the
response packet if the transaction is acknowledged with an ack_pending.
When DTSpDis is set to 1, the DTF packetizer does not wait for the response packet even if the transaction
is acknowledged with ack_pending.
89
DhdSel
R/W
DTx header select. 00: write request header, 01: DTF packetizer status, 10: read request header, 11: DRF
packetizer status
10
RconfSnglpkt
R/W
Receive confirm for each single packet. When RconfSnglpkt is set to 1, each quadlet read from the DRF
reflects the value of the DRF status. Otherwise DRF status is updated for every packet received. This bit
defaults to 1 and is unaffected by a bus reset.
11
LongBlk
R/W
Long block size. LongBlk determines whether the DTF_BlockSize or the DTF_BlockCount are used in
registers B0h and B4h.
12
QuadSend
R/W
Quadlet request send. When QuadSend is set to 1, the packetizer translates a 4-byte block request to a
quadlet request packet. When QuadSend is set to 0, a 4-byte block request is used. This bit defaults to 1
and is unaffected by a bus reset.
13
QuadBndry
R/W
When QuadBndry is set to 1, the packetizer aligns the quadlet address boundary in the first request
packet.
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