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| 型號(hào)： | TSB43AA82PGE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 95/146頁(yè) |
| 文件大?。?/td> | 770K |
| 代理商： | TSB43AA82PGE |
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326
3.4.32 DTF/DRF and DTF/DRF Page Table Size Register at 98h
This register defaults to 0000 0000h and is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
05
DTFPTBufSiz
R/W
DTF page table fetch buffer size. DTFPTBufSiz is the buffer size in quadlets for the DTF page table
fetching (see Note 1).
615
DTF_Size
R/W
DTF size control bits. DTF_Size is equal to the DTF size number in units of 4 quadlets.
1621
DRFPTBufSiz
R/W
DRF page table fetch buffer size. DRFPTBufSiz is the buffer size in quadlets for the DRF page table
fetching (see Note 1).
2231
DRF_Size
R/W
DRF size control bits. DRF_Size is equal to the DRF size number in units of 4 quadlets. These bits default
to 40h.
NOTE 1: RAM size (quadlets) is partitioned according to the following equation.
AR_CSR_Siz(8Ch)+DTFPTBufSiz(98h)+DRFPTBufSiz(98h)+MTTBufSiz(94h)+MTRBufSiz(94h)+LOGSize = 126 quadlets
3.4.33 DTF/DRF Available Register at 9Ch
This register defaults to 8000 C000h and, except for the specified bits, is unaffected by a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
0
DTFEmpty
R/O
DTF empty flag. DTFEmpty specifies the DTF status. When the DTF is empty, this bit is set to 1. This bit
defaults to 1 and is set to 1 on a bus reset.
13
Reserved
N/A
Reserved
415
DTFAvail
R/O
DTF available flag. DTF has space available for DTFAvail quadlets. Remaining size is displayed in
quadlets. These bits default to 0 and are unaffected by a bus reset.
16
DRFEmpty
R/O
DRF empty flag. DRFEmpty specifies the DRF status. When the DRF is empty, this bit is set to 1. This bit
defaults to 1 and is set to 1 on a bus reset.
17
BDOAvail
R/O
This bit reflects the status of BDOAVAIL terminal. Note: This bit is not always equal to BDOAVAIL output
because the polarity of BDOAVAIL is set by BOAvCtl (94h bit 13). This bit defaults to 1.
1819
Reserved
N/A
Reserved
2031
DRFThere
R/W
DRF there flag. The number of quadlets received in the DRF. These bits default to 0 and are unaffected by
a bus reset.
Note: Do not read out data more than the displayed size. (The numerical value of this counter de-
creases and becomes negative.)
3.4.34 DTF/DRF Acknowledge Register at A0h
This register defaults to 0000 0000h and is set to 0000 0000h on a bus reset.
BITS
ACRONYM
DIR
DESCRIPTION
06
Reserved
N/A
Reserved
7
DRAErr
R/O
DRF ack error. When the ack received has a parity error or length error, AckErr (E8h, bit 11) is set to 1.
When the ack has no errors or an ack has not been received yet, AckErr is set to 0.
811
DRxAck
R/O
DRF transmitter acknowledge received. The last ackcode received for a read request packet for the DRF.
The value is updated each time the ack is received.
1214
Reserved
N/A
Reserved
15
DRAVal
R/O
DRF ack valid. This bit specifies whether DRxAck has been already read. When DRxAck has not been
read, DRAVal is 1. When DRxAck has been read, DRAVal is 0.
1622
Reserved
N/A
Reserved
23
DTAErr
R/O
DTF ack error. When the ack received had a parity error or length error, AckErr (E8h, bit 11) is set to
1.When the ack has no error or an ack has not been received, AckErr is set to 0.
2427
DTxAck
R/O
DTF transmitter acknowledge received. The last ack code received for the packet transmitted from DTF.
The value is updated each time the ack is received.
2830
Reserved
N/A
Reserved
31
DTAVal
R/O
DTF ack valid. This bit specifies whether DtxAck has already been read. When DtxAck has not been read,
DTAVal is set to 1. When DtxAck has already been read, DTAVal is set to 0.
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