參數(shù)資料
型號： TSB43AA82PGE
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 127/146頁
文件大?。?/td> 770K
代理商： TSB43AA82PGE
61
6 Transaction Timer/Manager (TrMgr)
The timer manages all transmissions from transmitting FIFOs. Once the host writes packet data into a FIFO, no
control is needed until the transaction ends.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
29 30 31
60h
Transaction
timer
control
DTTxEd
DR
TxEd
A
TTxEd
MTTxEd
CTTxEd
AR
TxEd
DTErr
DRErr
A
TErr
MTErr
CTErr
ARErr
DTRtry
DRRtry
A
TRtry
MTRtry
CTRtry
ARRtry
Timer No.
TxAdbrr
HIdT
r
RIsT
r
64h
Transaction
timer
status1
destination ID
destination_offset_hi
68h
Transaction
timer
status2
destination_offset_lo
6Ch
Transaction
timer
status3
tCode
spd
tLabel
Retry_Counter
SplitTrTimer
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
29 30 31
6.1
Confirm Transaction End
Transaction end can be confirmed by checking DTTxEd, DRTxEd, ATTxEd, MTTxEd, CTTxEd, and ARTxEd in the
transaction timer control (60h). Each bit shows the status of the timer; a low bit indicates that a transaction is still in
progress.
6.2
Confirm End State
The end state can be confirmed by checking the XXErr bit of each timer status. The XXErr bit indicates the previous
transaction of this timer has ended in error. Additionally, the cause of the error can be identified by checking the status
of the response packet stored in the response FIFO.
NOTE: The response FIFO always stores a response packet with its status. Even when no
response packet was received due to BusyRetry or SplitTimeout, a dummy response packet
is stored with the status. The only exceptions are transactions erased by the host through an
abort or bus reset.
6.3
Confirm Status of Ongoing Transaction
The XXRtry bit of each status shows that a transaction is in progress. When a Rtry bit is not set and XXEd has not
been cleared, it is in split-transaction.
By checking transaction timer control register (60h), the detailed condition of a transaction can be confirmed. The
number on each timer, shown Table 6-1, is used to confirm transaction detail. The following is an example of checking
transaction detail:
To check detail status of CTQ, first write the appropriate timer number into TimrNO in the transaction timer
control register (60h). In this case number is 4 for CTQ. Then, check the transaction timer status registers
(64h6Ch). This shows the corresponding address, tLabel, speed and retry counter. Other timers can be
checked by the same method.
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